Analog Devices Inc. AD7721ANZ

Overview

AD7721ANZ from Analog Devices is a 16-bit sigma-delta analog-to-digital converter (ADC) with 468.75 kHz output word rate, 229.2 kHz input bandwidth, and integrated FIR digital filtering. It operates from a single +5 V supply, accepts differential analog inputs (0 V to 2.5 V or ±1.25 V), and features on-chip offset/gain calibration for dc accuracy. It is used in high-precision industrial data acquisition systems requiring low-power, high-linearity digitization of sensor signals.

For engineers reviewing the AD7721ANZ datasheet, AD7721ANZ pinout, AD7721ANZ application, or AD7721ANZ equivalent, this page delivers verified technical context, interface timing constraints, serial/parallel mode trade-offs, calibrated dc performance metrics, and real-world antialiasing filter design guidance - all specific to the AD7721ANZ plastic DIP package.

Technical Context

The AD7721ANZ employs a single-bit sigma-delta modulator followed by two cascaded finite impulse response (FIR) digital filters, enabling 16-bit resolution with no missing codes and linear-phase frequency response. Its analog input is continuously sampled at twice the master clock frequency (up to 30 MHz), eliminating external sample-and-hold circuitry.

It supports dual interface modes: serial mode (16-bit output, 15 MHz max CLK, internal SCLK generation) and parallel mode (12-bit output, 10 MHz max CLK, programmable control register). Calibration logic corrects offset and gain errors using on-chip registers, and standby mode reduces power to 100 µW by disabling modulator and filter clocks.

Key Specifications

Pinout & Package

AD7721ANZ is housed in a 28-pin plastic DIP (N-28) package with 0.6-inch width, through-hole mounting, and industry-standard pin spacing. Pin functions are electrically validated per Analog Devices AD7721 Rev. A datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar sigma-delta ADC applications.

Compared with AD7722BRUZ and ADS1258IPW, the AD7721ANZ uniquely balances 16-bit speed (468.75 kHz), on-chip FIR filtering, dual serial/parallel interfaces, and through-hole DIP packaging - making it optimal for legacy industrial designs requiring upgradeable, calibrated, high-throughput digitization without redesigning PCB layout.

Availability

AD7721ANZ is available at Aetrix Electronics and suitable for industrial process monitoring, portable medical instrumentation, ultrasonic transducer interface, and high-fidelity audio digitization requiring stable component supply and long-term obsolescence management.

Supply support for AD7721ANZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The AD7721ANZ belongs to Analog Devices' precision sigma-delta ADC product line, designed specifically for high-speed, low-power, calibrated data acquisition in industrial and instrumentation applications where dc accuracy and dynamic performance must coexist.

FAQ

What is the maximum clock frequency supported by AD7721ANZ in serial versus parallel mode?

The AD7721ANZ supports up to 15 MHz master clock frequency in serial mode for full 468.75 kHz output word rate and 229.2 kHz input bandwidth. In parallel mode, the maximum clock frequency is 10 MHz, yielding 312.5 kHz output word rate and reduced input bandwidth. Exceeding these limits violates timing specifications and may cause data corruption or invalid DRDY behavior. The AD7721ANZ datasheet specifies these values under "TIMING CHARACTERISTICS" for each interface mode.

Does AD7721ANZ require an external reference, and what are the acceptable voltage and current specifications?

Yes, the AD7721ANZ requires an external reference applied to the REFIN pin. The specified range is 2.4 V to 2.6 V, with 2.5 V nominal. The device draws up to 200 µA from REFIN, so the reference source must be stable, low-noise, and capable of sourcing this current without droop. A 100 nF decoupling capacitor between REFIN and AGND is mandatory per the AD7721ANZ datasheet to ensure reference integrity during digital switching events.

How does the AD7721ANZ handle input overrange conditions, and what role does the DVAL pin play?

The AD7721ANZ uses the DVAL pin to signal overrange events. When input exceeds ±1.25 V (bipolar) or 0–2.5 V (unipolar), DVAL goes low: small overloads cause output clipping to full scale; large overloads trigger internal modulator reset and hold DVAL low for 2080 clock cycles while output registers are set to negative full scale. This behavior is documented in the "USING THE AD7721" section of the AD7721ANZ datasheet and enables robust fault detection in real-time systems.

Can AD7721ANZ operate with a single +5 V supply, and how are AVDD and DVDD configured?

Yes, the AD7721ANZ operates from a single +5 V ±5% supply, but it requires separate AVDD and DVDD pins both tied to +5 V. AVDD powers the analog modulator and reference circuitry; DVDD powers digital logic and I/O buffers. Although supplied from the same rail, AVDD and DVDD must be decoupled independently with low-ESR capacitors to prevent digital noise from coupling into the analog path. This dual-supply pinout is explicitly defined in the AD7721ANZ functional block diagram and pin descriptions.

What is the purpose of the DSUBST pin on AD7721ANZ, and how must it be connected?

The DSUBST pin is the substrate connection for the AD7721ANZ's digital circuits and must be connected via its own short, low-inductance trace directly to AGND (Pin 24), not DGND. This connection prevents latch-up and minimizes substrate noise coupling into sensitive analog sections. The AD7721ANZ datasheet mandates this routing in the "PIN FUNCTION DESCRIPTIONS" section and warns that improper DSUBST grounding degrades CMRR and introduces offset drift - a requirement unique to this device's mixed-signal layout.