Analog Devices Inc. AD7721AR

Overview

AD7721AR from Analog Devices is a low-power, 16-bit sigma-delta analog-to-digital converter with 468.75 kHz output word rate, 229.2 kHz input bandwidth, and on-chip dual FIR filtering. It operates from +5 V supplies, accepts differential analog inputs (±1.25 V or 0 V to 2.5 V), and features internal offset/gain calibration for ±4.88 mV full-scale error. It serves in high-accuracy industrial data acquisition systems requiring continuous sampling without external S/H.

For engineers reviewing the AD7721AR datasheet, AD7721AR pinout, AD7721AR application, or AD7721AR equivalent, this page delivers verified technical context, interface timing constraints, calibrated DC accuracy metrics, serial/parallel mode trade-offs, and real-world antialiasing design guidance - all specific to the AD7721AR SOIC-28 variant.

Technical Context

The AD7721AR uses a single-bit sigma-delta modulator with on-chip calibration of offset and gain registers, ensuring endpoint accuracy without external trimming. Its dual cascaded FIR filters provide linear-phase response and reduce external antialiasing to first-order RC requirements.

It supports two distinct interface modes: serial mode (15 MHz max CLK, master clock provided on SCLK/DB7) and parallel mode (10 MHz max CLK, 12-bit resolution at 312.5 kHz OWR). Mode selection is determined at power-up via CS/RD/WR logic states, and configuration bits (e.g., UNI/DB2, CAL/DB1, STBY/DB0) control bipolar/unipolar range, calibration initiation, and standby entry.

Key Specifications

Pinout & Package

AD7721AR is housed in a 28-pin 0.3" wide SOIC package (R-28), with separate analog (AGND) and digital (DGND) ground pins, substrate tie (DSUBST), and dedicated supply pins (AVDD, DVDD).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar sigma-delta ADC applications.

Compared with AD7722AR and ADS1258IPW, the AD7721AR uniquely balances 16-bit resolution, 468.75 kHz output rate, on-chip dual FIR filtering, and dual serial/parallel interface - making it the only option among the three that meets simultaneous high-speed, high-accuracy, and minimal external component requirements.

Availability

AD7721AR is available at Aetrix Electronics and suitable for industrial process monitoring, medical instrumentation, energy metering subsystems, and test & measurement equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD7721AR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The AD7721AR belongs to Analog Devices' precision sigma-delta ADC product line, designed specifically for high-accuracy, medium-bandwidth data acquisition in industrial and instrumentation applications where on-chip filtering and calibration reduce system complexity.

FAQ

What is the maximum clock frequency supported by the AD7721AR in serial versus parallel mode?

The AD7721AR supports a maximum master clock frequency of 15 MHz in serial mode and 10 MHz in parallel mode. At 15 MHz serial clock, the device achieves its rated 468.75 kHz output word rate and 229.2 kHz input bandwidth. In parallel mode, the 10 MHz limit yields a 312.5 kHz output word rate and 152.8 kHz bandwidth. Exceeding these frequencies violates timing specifications and may cause data corruption or loss of guaranteed performance.

How does the AD7721AR handle analog input overrange conditions?

The AD7721AR uses the DVAL pin (or DVAL/SYNC pin configured as DVAL) to flag overrange events. Small overloads clip output to positive or negative full scale while holding DVAL low. For large overloads causing modulator instability - which can occur beyond ±20% of full scale within the input bandwidth - internal detection resets the modulator and holds DVAL low for 2080 clock cycles while output registers are set to negative full scale. DRDY continues asserting valid data during this period.

Does the AD7721AR require an external sample-and-hold circuit?

No, the AD7721AR does not require an external sample-and-hold circuit. Its analog modulator continuously samples the input at twice the master clock frequency (e.g., 30 MHz at 15 MHz CLK), inherently performing oversampling. This architecture, combined with on-chip FIR filtering, shifts antialiasing requirements from the analog domain to a relaxed first-order RC filter - eliminating S/H complexity, cost, and aperture jitter limitations.

What is the purpose of the DSUBST pin on the AD7721AR, and how must it be connected?

The DSUBST pin is the substrate connection for the AD7721AR's digital circuitry. It must be connected via its own short, low-inductance trace directly to AGND (Pin 24), not to DGND or any other node. This dedicated path prevents digital switching noise from coupling into the analog ground plane and degrading AC performance (e.g., SNR, THD) or introducing offset drift. Failure to isolate DSUBST properly risks violating the specified 74 dB SNR minimum.

Can the AD7721AR operate with a reference voltage other than 2.5 V?

Yes, the AD7721AR accepts a reference voltage (REFIN) between 2.4 V and 2.6 V. While 2.5 V is nominal and commonly used with references like the AD780, operation at 2.45 V or 2.55 V is fully specified. The full-scale input range scales linearly with VREFIN: unipolar mode becomes 0 V to VREFIN, bipolar mode becomes ±VREFIN/2. All DC accuracy specs (e.g., ±4.88 mV full-scale error) remain valid across this range, as gain calibration is performed relative to the applied REFIN voltage.