Analog Devices Inc. AD7721ARZ

Overview

AD7721ARZ from Analog Devices is a 16-bit sigma-delta analog-to-digital converter (ADC) with 468.75 kHz output word rate, 229.2 kHz input bandwidth, and integrated dual-stage FIR digital filtering. It operates from +5 V supplies, accepts differential analog inputs (0 V to 2.5 V or ±1.25 V), and features on-chip offset/gain calibration for <±4.88 mV full-scale error. It serves in high-accuracy industrial data acquisition systems requiring low missing-code risk and linear-phase response.

For engineers reviewing the AD7721ARZ datasheet, AD7721ARZ pinout, AD7721ARZ application, or AD7721ARZ equivalent, key selection considerations include its dual-mode serial/parallel interface, 15 MHz max master clock (serial), 10 MHz max (parallel), standby power of 100 µW, and differential nonlinearity of ±8 LSB (16-bit mode).

Technical Context

The AD7721ARZ employs a single-bit sigma-delta modulator with on-chip calibration logic that corrects offset and gain errors by loading correction values into internal registers. Its two cascaded finite impulse response (FIR) filters provide linear-phase, low-pass response with group delay of 48.53 µs at 15 MHz clock.

It supports both unipolar (0 V to VREFIN) and bipolar (±VREFIN/2) input ranges via the UNI/DB2 pin, and offers configurable operation modes: serial (master-clock-driven SCLK output, DRDY-rising-edge data ready) and parallel (CS/RD/WR-controlled, DRDY-falling-edge data ready). Calibration and synchronization are initiated via dedicated CAL/DB1 and SYNC/DB5 pins.

Key Specifications

Pinout & Package

AD7721ARZ is housed in a 28-lead SOIC (R-28) package with exposed pad (not electrically connected). Pin functions are validated per Analog Devices AD7721 Rev. A datasheet, with strict separation between analog (AVDD, AGND, VIN1/VIN2, REFIN) and digital (DVDD, DGND, DBx, CLK, DRDY) domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar sigma-delta ADC applications.

Compared with AD7722ARZ and ADS1258IPWR, the AD7721ARZ uniquely balances 16-bit accuracy, 468.75 kHz throughput, and dual serial/parallel interfacing - making it optimal for industrial DAQ systems requiring deterministic timing and MCU compatibility without protocol translation.

Availability

AD7721ARZ is available at Aetrix Electronics and suitable for industrial process monitoring, medical instrumentation, energy metering, and test & measurement equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD7721ARZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The AD7721ARZ belongs to Analog Devices' precision sigma-delta ADC product line, designed specifically for high-accuracy, low-power data acquisition in industrial and medical instrumentation where dc accuracy, noise performance, and interface flexibility are critical.

FAQ

What is the maximum master clock frequency supported by the AD7721ARZ in serial mode?

The AD7721ARZ supports a maximum master clock frequency of 15 MHz in serial mode, which yields its rated 468.75 kHz output word rate and 229.2 kHz input bandwidth. Operation above 15 MHz is not characterized or guaranteed; timing violations may occur beyond this limit. The AD7721ARZ datasheet specifies tCLK HI and tCLK LO minimums based on this 15 MHz ceiling.

Does the AD7721ARZ require an external antialiasing filter?

Yes, the AD7721ARZ requires an external antialiasing filter, though its on-chip FIR filtering relaxes requirements significantly. A simple first-order RC filter (e.g., 50 Ω + 7.84 nF for f_3dB ≈ 406 kHz) provides 31.1 dB attenuation at the first image frequency when fCLK = 15 MHz. This is far less demanding than the high-order filters needed for Nyquist-rate ADCs.

How does calibration affect the accuracy of the AD7721ARZ?

Calibration in the AD7721ARZ loads offset and gain correction values into internal registers, reducing full-scale error to ≤±4.88 mV and offset error to ≤±3.66 mV. These corrections are applied in real time: the offset register is subtracted from the filter output, then multiplied by the gain factor. Calibration must be performed at the target operating temperature for best results.

Can the AD7721ARZ operate with a 3.3 V supply?

No, the AD7721ARZ is specified only for +5 V ±5% supplies (AVDD and DVDD = 4.75 V to 5.25 V). Its absolute maximum ratings allow up to +7 V, but functional operation below 4.75 V is not guaranteed. Logic thresholds (e.g., VINH = 2.0 V) and analog performance (e.g., reference compliance, INL) are validated exclusively at 5 V.

What is the purpose of the DSUBST pin on the AD7721ARZ?

The DSUBST pin is the substrate connection for the AD7721ARZ's digital circuitry and must be connected via a short, low-inductance path to AGND (Pin 24). This connection minimizes substrate coupling noise between analog and digital sections, preserving CMRR (>70 dB) and preventing digital switching transients from corrupting analog measurements.