Analog Devices Inc. AD775JN

Overview

AD775JN from Analog Devices is a CMOS 8-bit, 20 MSPS sampling analog-to-digital converter (ADC) with pipelined/ping-pong two-step flash architecture, differential nonlinearity of ±0.3 LSB (typ), 60 mW power dissipation at +5 V, and video industry standard pinout. It operates over –20°C to +75°C and supports ground-inclusive input ranges via on-chip reference bias resistors - ideal for portable video digitization and real-time image acquisition systems.

For engineers reviewing the AD775JN datasheet, AD775JN pinout, AD775JN application, or AD775JN equivalent, key selection considerations include its 20 MSPS maximum conversion rate, 11 pF analog input capacitance, single +5 V supply operation, differential gain/phase errors of 1.0% / 0.5°, and compatibility with video signal chains requiring low-power, high-speed digitization without external sample-and-hold.

Technical Context

The AD775JN implements a pipelined two-step subranging flash architecture where coarse comparators resolve the top four MSBs and fine comparators resolve the bottom four LSBs in alternating clock cycles ("ping-pong"), enabling continuous 20 MSPS sampling with 2.5-clock-cycle pipeline latency. Its switched-capacitor input acquires on the falling clock edge, eliminating need for external SHA.

Reference ladder configuration supports multiple topologies: self-biased (VRTS→VRT, VRBS→VRB) yields ~0.64 V to 2.73 V span; VRB tied to AVSS enables 0 V–2.4 V ground-referenced input. Input linearity depends on VRT–VRB span ≥1.8 V, and aperture jitter is specified at 30 ps.

Key Specifications

Pinout & Package

AD775JN is packaged in a 24-pin 400 mil plastic DIP (N-24B), with separate analog/digital supplies (AVDD/DVDD, AVSS/DVSS) and dedicated reference bias pins (VRTS, VRBS) enabling flexible ladder configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit, 20+ MSPS ADC applications.

Compared with AD9203ARUZ and MAX1186ECM+, the AD775JN uniquely combines video-optimized analog performance (1% differential gain), self-biased reference ladder, and 24-pin DIP package for through-hole prototyping - making it irreplaceable in legacy +5 V video digitization where pinout, supply, and feature alignment are critical.

Availability

AD775JN is available at Aetrix Electronics and suitable for video digitization, medical imaging acquisition, industrial machine vision, and portable test equipment requiring stable component supply across extended commercial temperature range (–20°C to +75°C).

Supply support for AD775JN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing ICs for precision instrumentation, communications, and industrial applications.

The AD775JN belongs to Analog Devices' legacy high-speed ADC product line, designed specifically for cost-effective, low-power video and imaging digitization in +5 V systems with emphasis on differential gain/phase accuracy and ease of reference configuration.

FAQ

What is the maximum sampling rate supported by the AD775JN?

The AD775JN supports a maximum conversion rate of 20 MSPS under standard conditions (TA = +25°C, AVDD/DVDD = +5 V). It can operate up to 35 MHz in optimized environments, but performance metrics such as SNR degrade above 20 MSPS - particularly with increasing temperature or decreasing supply voltage. The AD775JN datasheet specifies 20 MSPS as the guaranteed operational limit for full specification compliance, including differential gain error ≤1.0% and DNL ≤±0.5 LSB.

Does the AD775JN require an external sample-and-hold amplifier?

No, the AD775JN does not require an external sample-and-hold amplifier. Its switched-capacitor input architecture inherently performs sampling on the falling edge of the CLK signal, and the pipelined two-step flash design integrates acquisition functionality. This is confirmed in the "PRODUCT DESCRIPTION" and "THEORY OF OPERATION" sections of the AD775JN datasheet, which explicitly state "no external SHA is required." The AD775JN's 11 pF input capacitance further simplifies driving requirements compared to conventional flash ADCs.

How is the reference voltage configured on the AD775JN?

The AD775JN supports two primary reference configurations using on-chip bias resistors: (1) self-biased mode, where VRTS (Pin 16) is shorted to VRT (Pin 17) and VRBS (Pin 22) is shorted to VRB (Pin 23), yielding ~0.64 V to 2.73 V input span; and (2) ground-referenced mode, where VRB (Pin 23) is tied to AVSS (0 V) and VRT (Pin 17) is driven via VRTS (Pin 16), giving 0 V to +2.4 V span. Both configurations are detailed in Figures 8 and 9 of the AD775JN datasheet, and decoupling capacitors are required at VRT and VRB pins to minimize noise.

What is the significance of the 11 pF analog input capacitance in AD775JN system design?

The 11 pF analog input capacitance of the AD775JN significantly reduces the drive strength required from preceding circuitry - enabling direct interface with low-power op-amps like the AD817 without additional buffering stages. As stated in the "ANALOG INPUT" section, this capacitance comprises both parasitic and switched-capacitor elements, and accurate acquisition to 1/4-bit resolution within 20 ns demands source impedance <100 Ω. This value directly impacts layout decisions, such as minimizing trace length and avoiding stubs, and is a key differentiator versus higher-capacitance flash ADCs that necessitate more complex driver networks.

Can the AD775JN operate with a 0 V to +2.4 V input range?

Yes, the AD775JN can operate with a 0 V to +2.4 V input range by connecting VRB (Pin 23) to AVSS (0 V) and using VRTS (Pin 16) to bias VRT (Pin 17), as shown in Figure 9 of the AD775JN datasheet. This configuration leverages the on-chip reference bias resistors to generate a ground-inclusive span suitable for dc-coupled video and imaging signals. The datasheet confirms this topology delivers nominal 0 V–2.4 V range at AVDD = +5 V, and specifies that input spans below 1.8 V may degrade DNL performance - so 2.4 V satisfies the minimum recommended span.