Analog Devices Inc. AD7822BN
- Part No.:
- AD7822BN
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
AD7822BN.pdf
- Description:
- IC ADC 8BIT 1CH 2MSPS 20-DIP
- Quantity:
- Payment:

- Shipping:

Inventory:7,767
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD7822BN from Analog Devices is a high-speed, single-channel, 8-bit analog-to-digital converter (ADC) with 420 ns conversion time, 2 MSPS throughput, on-chip 2.5 V reference, and track-and-hold amplifier. It operates from 3 V ±10% or 5 V ±10% supply and supports standalone operation via EOC pulse for data acquisition in DSP front ends and mobile communication systems.
For engineers reviewing the AD7822BN datasheet, AD7822BN pinout, AD7822BN application, or AD7822BN equivalent, key selection considerations include its 1-channel configuration, automatic power-down triggered by CONVST logic level at EOC, VMID-adjustable input span (0 V to 2 V @ 3 V, 0 V to 2.5 V @ 5 V), and compatibility with microprocessor parallel interfaces requiring minimal address decoding.
Technical Context
The AD7822BN implements an 8-bit half-flash architecture: a 4-bit flash ADC generates MSBs, followed by a second flash stage for LSBs-achieving full conversion within 420 ns. Its track-and-hold acquires input in ≤200 ns and supports full-power bandwidth up to 10 MHz, enabling subsampling of RF/IF signals.
It integrates a 2.5 V ±2% on-chip reference, flexible analog input scaling via VMID (adjustable centering from AGND to VDD), and dual power-down control-automatic (via CONVST sampling at EOC high) and explicit (via dedicated PD pin). Logic interface complies with 3 V/5 V TTL levels and features high-impedance outputs with bus relinquish timing independent of external load capacitance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 8-bit - guarantees no missing codes over full temperature range (−40°C to +85°C) |
| Conversion Time | 420 ns max - enables 2 MSPS sustained throughput with deterministic timing |
| Analog Input Span | 0 V to 2.5 V p-p @ 5 V supply or 0 V to 2 V p-p @ 3 V supply - auto-detected by internal VDD comparator |
| On-Chip Reference | 2.5 V ±2% - eliminates need for external reference; usable as VREF IN/OUT or left floating |
| Power Consumption | 12 mA max @ 5 V normal operation; 5 μA max in power-down - supports low-duty-cycle sampling |
| Channel Count | 1 single-ended input (VIN1 only) - fixed channel count; no multiplexer address pins required |
| SNR @ 30 kHz | 48 dB min - sufficient for medium-fidelity signal digitization in disk drive servo loops |
Pinout & Package
AD7822BN is housed in a 20-lead, 0.3" wide plastic dual in-line package (PDIP), with pin 1 identified by notch or dot. All pins are electrically defined per Analog Devices Rev. C datasheet; no NC (no-connect) pins present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 DB2 | Data Output Bit 2 | LSB-aligned parallel output line; tri-state when RD or CS high |
| 2 DB1 | Data Output Bit 1 | Part of 8-bit unidirectional data bus; driven only during valid read cycle |
| 3 DB0 | Data Output Bit 0 | Provides LSB of conversion result; synchronized to RD falling edge |
| 4 CONVST | Convert Start / Power-Down Control | Falling edge initiates conversion; sampled at EOC high to enter automatic power-down |
| 5 CS | Chip Select | Enables parallel port; must be low with RD to drive DB0–DB7 onto shared bus |
| 6 RD | Read Strobe | Falling edge latches conversion result onto data bus; defines t9 data access window (10 ns @ 3 V) |
| 7 DGND | Digital Ground | Reference for all digital I/O; isolated from AGND but tied at single point per layout best practice |
| 8 EOC | End-of-Conversion Output | Active-low pulse (70–110 ns wide); used to trigger MCU interrupt or latch data |
| 9 PD | Power-Down Input | Direct control: logic low forces immediate power-down; logic high resumes operation |
| 10 NC | No Connect | Not bonded; must remain unconnected per datasheet - no routing or pull-up/pull-down |
| 11 VIN1 | Analog Input Channel 1 | Single-ended input; full-scale range set by VDD and VMID voltage |
| 12 VMID | Input Span Center Reference | Sets midpoint of analog input range (e.g., 1.0 V @ 3 V); default = VDD/2 if open |
| 13 VREF IN/OUT | Reference Voltage Terminal | Supplies or sinks 2.5 V reference; decoupling capacitor recommended if using internal ref |
| 14 VDD | Positive Supply | Accepts 2.7–3.3 V or 4.5–5.5 V; powers analog and digital sections simultaneously |
| 15 AGND | Analog Ground | Reference for T/H, comparator, reference circuit; separate from DGND but connected at star point |
| 16 DB7 | Data Output Bit 7 | MSB of conversion result; valid after t9 delay following RD falling edge |
| 17 DB6 | Data Output Bit 6 | Part of synchronous 8-bit parallel output; timing-critical for high-speed interfacing |
| 18 DB5 | Data Output Bit 5 | Driven only when both RD and CS are asserted; high-impedance otherwise |
| 19 DB4 | Data Output Bit 4 | Ensures deterministic setup/hold margins for microprocessor or FPGA capture |
| 20 DB3 | Data Output Bit 3 | Completes 8-bit data word; all bits updated simultaneously at end of conversion |
Key Features
| Feature | Design Value |
|---|---|
| 420 ns conversion time | Enables real-time DSP processing with ≥1.5 μs available per sample at 2 MSPS |
| VMID-adjustable input span | Allows offset compensation without external op amps - reduces BOM count in single-supply systems |
| Automatic power-down on CONVST | Reduces average current to <1 μA between conversions without software overhead or extra control lines |
| On-chip 2.5 V reference (±2%) | Eliminates external reference IC and associated decoupling; simplifies layout and improves system SNR stability |
| Full-power bandwidth ≥10 MHz | Supports undersampling of IF signals up to 10 MHz - suitable for mobile comms receiver front ends |
Applications
| High-Speed Data Acquisition | Disk Drive Servo Control |
|---|---|
Use Scenario: Real-time monitoring of motor position feedback and head actuator current in HDD servo loops. IC Role / Device Role / Timing Role: Single-channel ADC digitizing analog sensor outputs at 2 MSPS with sub-microsecond latency. Use Value: 420 ns conversion time ensures tight closed-loop timing; 8-bit resolution meets servo error detection requirements without oversampling. |
Use Scenario: Digitizing voice-band audio and control signals in portable disk drive electronics. IC Role / Device Role / Timing Role: Low-latency ADC capturing analog signals from spindle motor drivers and read/write channel sensors. Use Value: Automatic power-down reduces idle current; VMID adjustment accommodates varying sensor offsets across production units. |
| Mobile Communication Subsampling | DSP Front-End Interface |
Use Scenario: Direct IF sampling in GSM/EDGE receiver architectures where 10 MHz full-power bandwidth is critical. IC Role / Device Role / Timing Role: ADC performing undersampling of 45–90 MHz IF signals down to baseband-compatible rates. Use Value: 10 MHz FPBW enables faithful capture of modulated carriers; 2 MSPS rate matches common DSP decimation stages. |
Use Scenario: Interfacing analog sensors and transducers to TI C5000 or ADI SHARC DSPs via parallel bus. IC Role / Device Role / Timing Role: Microprocessor-compatible ADC providing EOC-synchronized data ready signal for DMA-triggered reads. Use Value: EOC pulse allows zero-wait-state operation; parallel interface requires only CS/RD/CONVST - no address latching needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7825BN | 4-channel version with A0/A1 address inputs; identical conversion speed, reference, and power-down behavior | Requires external channel selection logic; not pin-compatible due to added pins and different pinout | Select AD7825BN only when multi-channel sampling with shared timing is required - not a drop-in replacement |
| MAX1186BCPP+ | 8-bit, 2 MSPS, 4-channel ADC with internal reference; uses SPI interface instead of parallel; no VMID pin | Lacks analog input span adjust and standalone EOC operation; requires serial controller resource | Choose MAX1186BCPP+ only for space-constrained designs accepting serial interface trade-offs and sacrificing VMID flexibility |
Compared with AD7825BN and MAX1186BCPP+, the AD7822BN uniquely delivers single-channel simplicity, VMID-based input offset tuning, and true parallel bus autonomy - making it optimal for cost-sensitive, low-pin-count, high-throughput embedded acquisition where channel count is fixed and analog conditioning is minimal.
Availability
AD7822BN is available at Aetrix Electronics and suitable for high-speed data acquisition systems, disk drive servo control, and mobile communication subsampling applications requiring stable component supply and long-term industrial availability.
Supply support for AD7822BN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD7822BN belongs to the AD782x family of high-speed, microprocessor-compatible sampling ADCs designed specifically for real-time signal acquisition in DSP front ends, disk drives, and portable communications equipment.
FAQ
What is the maximum sampling rate supported by the AD7822BN?
The AD7822BN supports a maximum throughput of 2 MSPS, enabled by its 420 ns maximum conversion time. This rate is achievable across the full industrial temperature range (−40°C to +85°C) and under both 3 V and 5 V supply conditions, provided timing constraints (e.g., t2 ≥20 ns CONVST pulse width, t3 ≥30 ns RD-to-CONVST spacing) are met per the Rev. C datasheet.
Does the AD7822BN require an external reference voltage?
No, the AD7822BN does not require an external reference voltage. It integrates a 2.5 V ±2% on-chip reference accessible at the VREF IN/OUT pin. The internal reference can be used directly - the pin may be left unconnected or decoupled to AGND with a 0.1 µF capacitor. An external reference may be applied only if higher accuracy or different voltage is needed.
How does the automatic power-down function work on the AD7822BN?
The AD7822BN enters automatic power-down when the CONVST pin is sampled low at the moment the EOC signal goes high (end of conversion). This feature eliminates the need for separate power-control logic. The device remains powered down until the next falling edge on CONVST initiates a new conversion, reducing average current to ≤0.2 µA in idle periods.
Can the AD7822BN interface directly with a 3.3 V microcontroller?
Yes, the AD7822BN supports 3 V ±10% operation and specifies logic input thresholds compatible with 3.3 V systems: VINH ≥2.0 V and VINL ≤0.4 V. Its DB0–DB7 outputs drive ≥2.4 V high and ≤0.2 V low at 200 µA load, meeting 3.3 V CMOS input requirements. No level-shifting circuitry is needed when interfacing with 3.3 V microcontrollers.
What is the purpose of the VMID pin on the AD7822BN?
The VMID pin sets the center voltage of the AD7822BN's analog input range. With VDD = 3 V, default span is 0 V to 2 V (centered at 1.0 V); with VDD = 5 V, it is 0 V to 2.5 V (centered at 1.25 V). Connecting VMID to a precise voltage shifts this center point anywhere between AGND and VDD - enabling offset correction for single-supply sensor interfaces without external op amps.
AD7822BN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Bits:
- 8
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- Parallel
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 1
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 20-PDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
AD7822BN FAQ
1.How can I place an order for AD7822BN through Aetrix?
Please submit a Request for Quotation (RFQ) for AD7822BN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD7822BN reliable?
The price and inventory of AD7822BN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD7822BN is usually 5 days.
3.What payment methods are accepted for AD7822BN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD7822BN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD7822BN?
AD7822BN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD7822BN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD7822BN?
For technical support, including AD7822BN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD7822BN requirements.
6.How does Aetrix verify that AD7822BN is sourced from the original manufacturer or authorized distributors?
All AD7822BN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD7822BN meets industry standards.
7.What is the process for return or replacement of AD7822BN?
All AD7822BN units undergo pre-shipment inspection (PSI). If there is an issue with AD7822BN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD7822BN part is unused and in its original packaging.
Return procedure for AD7822BN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD7822BN Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

