Analog Devices Inc. AD7859BSZ

Overview

AD7859BSZ from Analog Devices is a 12-bit, 8-channel, 200 kSPS sampling ADC with integrated track-and-hold, self- and system-calibration, and flexible parallel interface. It operates from a single 3 V to 5.5 V supply, delivers 71 dB SNR at 10 kHz input, supports unipolar (0 to VREF) and bipolar (±VREF/2) input ranges, and targets precision data acquisition in battery-powered instrumentation.

For engineers reviewing the AD7859BSZ datasheet, AD7859BSZ pinout, AD7859BSZ application, or AD7859BSZ equivalent, key selection considerations include its 44-pin PQFP package, 16-bit/8-bit parallel I/O support, 0.5 µs track/hold acquisition time, and dual power management modes enabling 1.3 mW operation at 10 kSPS.

Technical Context

The AD7859BSZ employs a charge redistribution SAR architecture with on-chip calibration memory and controller, enabling both self-calibration (offset/gain) and system-level calibration. Its pseudo-differential input multiplexer supports eight single-ended or four differential channel configurations via software-controlled register writes.

Conversion timing is synchronized to an external master clock (up to 4 MHz), with fixed 18-clock-cycle conversion time (4.5 µs). The parallel interface includes RD/WR/CS control with W/B-selectable 16-bit word or 8-bit byte transfer, and BUSY/CONVST signals for precise timing coordination in embedded systems.

Key Specifications

Pinout & Package

AD7859BSZ is housed in a 44-pin plastic quad flatpack (PQFP) package, RoHS-compliant, with 0.8 mm lead pitch and exposed thermal pad (not electrically connected). Pin 1 identified by top-side marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 12-bit, multi-channel ADC applications.

Compared with AD7859ASZ and ADS7822U, the AD7859BSZ provides superior DC accuracy (±0.5 LSB INL), integrated reference, and parallel interface flexibility-making it optimal for applications demanding guaranteed linearity, minimal external components, and host processor agnosticism.

Availability

AD7859BSZ is available at Aetrix Electronics and suitable for battery-powered medical instrumentation, industrial process monitoring, high-speed data acquisition for test equipment, and pen-based computing interfaces requiring stable component supply across extended product lifecycles.

Supply support for AD7859BSZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD7859BSZ belongs to Analog Devices' precision data acquisition ADC family, designed specifically for low-power, high-accuracy multichannel sampling in portable and industrial instrumentation where calibration integrity and supply flexibility are critical.

FAQ

What is the maximum master clock frequency supported by the AD7859BSZ?

The AD7859BSZ supports a maximum master clock (CLKIN) frequency of 4 MHz, which determines conversion timing (18 × t_CLKIN = 4.5 µs). Operation above this frequency violates timing specifications and may cause incorrect code generation or BUSY signal misalignment. The device is fully characterized at 4 MHz with 3 V or 5 V supply; lower frequencies (e.g., 1.8 MHz) are permitted but reduce throughput proportionally. Always verify clock duty cycle (40/60 to 60/40) and edge monotonicity per the AD7859BSZ datasheet timing diagrams.

Does the AD7859BSZ require external reference components?

Yes, the AD7859BSZ requires two external decoupling capacitors on its reference pins: a 0.1 µF multilayer ceramic capacitor (CREF1) between CREF1 and AGND, and a 0.01 µF ceramic disc capacitor (CREF2) between CREF2 and AGND. These stabilize the internal 2.5 V reference and suppress switching noise during conversion. While the part provides a 2.5 V REFOUT, using an external precision reference (e.g., ADR421) on REFIN/REFOUT is permissible and improves absolute accuracy-but mandates removal of CREF1/CREF2 and adherence to external reference drive capability limits.

How does the AD7859BSZ handle bipolar versus unipolar input configurations?

The AD7859BSZ supports both unipolar (0 to VREF) and bipolar (±VREF/2) input ranges via the AMODE bit in the control register. In unipolar mode (AMODE = 0), the output coding is straight binary; in bipolar mode (AMODE = 1), it uses 2's complement. For bipolar operation, AIN(–) must be biased to +VREF/2 (e.g., via resistor divider), and AIN(+) must remain within 0 V to AVDD. The AD7859BSZ does not include internal level-shifting circuitry-external biasing is required to meet the specified input voltage constraints and avoid clipping or damage.

Can the AD7859BSZ perform system calibration with an external reference?

Yes, the AD7859BSZ supports system calibration using an external reference applied to REFIN/REFOUT. During system calibration, the device measures actual offset and full-scale errors relative to the external reference and stores correction coefficients in on-chip calibration memory. This compensates for errors introduced by external signal conditioning (e.g., PGA gain error, sensor offset), provided the system-level offset span is within ±0.05 × VREF and full-scale span within +1.025/–0.975 × VREF. System calibration is initiated via CAL pin or CALMD bit and requires user-provided known reference voltages.

What is the function of the W/B pin on the AD7859BSZ?

The W/B (Word/Byte) pin on the AD7859BSZ selects the data bus transfer mode: logic high enables 16-bit word transfers on DB0–DB15, while logic low enables 8-bit byte transfers on DB0–DB7 with DB8 functioning as HBEN (High Byte Enable). In byte mode, the low byte must be written first, then the high byte. This allows seamless integration with both 8-bit and 16-bit microcontrollers without external bus-width translation logic. The W/B state is sampled at the rising edge of CS and remains latched until the next CS assertion.