Analog Devices Inc. AD7872BR-REEL
- Part No.:
- AD7872BR-REEL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AD7872BR-REEL.pdf
- Description:
- IC ADC 14BIT SAR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,339
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD7872BR-REEL from Analog Devices is a complete monolithic 14-bit successive approximation analog-to-digital converter (ADC) with integrated track-and-hold amplifier, 3 V buried Zener reference, and serial-only digital interface. It operates from ±5 V supplies, accepts bipolar ±3 V analog inputs, delivers 83 kSPS throughput, achieves 80 dB SNR at 10 kHz, and features 57 ns data access time. It is used in high-speed DSP servo control and spectrum analysis systems requiring precise timing and low-noise conversion.
For engineers reviewing the AD7872BR-REEL datasheet, AD7872BR-REEL pinout, AD7872BR-REEL application, or AD7872BR-REEL equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternative parts with documented functional differences, and supply-chain support details specific to industrial embedded and signal acquisition designs.
Technical Context
The AD7872BR-REEL implements a self-contained LC2MOS SAR architecture with on-chip laser-trimmed 2 MHz clock, eliminating external timing components. Its track-and-hold acquires signals to 14-bit accuracy in ≤2 μs, and internal 3 V reference exhibits ±40 ppm/°C tempco with 500 μA load capability.
It supports only serial output via three-wire interface (SSTRB, SCLK, SDATA), where data is valid on the falling edge of SCLK under active-low SSTRB framing. Conversion is initiated exclusively by CONVST rising edge, and BUSY/INT is not present-operation is strictly Mode 1 with asynchronous start and serial readback.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - guarantees no missing codes; enables 366 μV LSB step size over ±3 V input range. |
| Throughput Rate | 83 kSPS - determined by 10.5–11 μs conversion time plus track-and-hold acquisition; supports real-time DSP sampling up to 41.5 kHz full-power bandwidth. |
| SNR @ 10 kHz | 80 dB min - includes distortion and noise; sufficient for 13.5 ENOB in audio and communications applications. |
| Analog Input Range | ±3 V bipolar - compatible with standard op-amp signal conditioning stages; requires no external reference or scaling resistors for basic operation. |
| Reference Output | 3.00 V ±10 mV @ +25°C - internally trimmed buried Zener; stable enough to serve as precision external reference for companion DACs or sensors. |
| Power Dissipation | 50 mW typ - achieved at ±5 V supplies; enables thermal management in dense mixed-signal PCB layouts without forced air. |
| Digital Interface | 3-wire serial (SSTRB/SCLK/SDATA) - open-drain SCLK and pull-up–required SSTRB/SDATA simplify isolation and level-shifting in multi-voltage systems. |
Pinout & Package
AD7872BR-REEL is housed in a 16-pin SOIC package (body width 3.9 mm, JEDEC MS-012AC). Pin 1 is CONTROL; pin 16 is VDD (tied to pin 9). All pins are electrically defined per Analog Devices Rev. F datasheet, with no NC pins except pin 7 and pin 10.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CONTROL) | Serial clock gating control | Selects continuous (−5 V) or gated (0 V) SCLK output; determines serial frame timing behavior and bus loading profile. |
| 2 (CONVST) | Asynchronous conversion trigger | Rising-edge–initiated hold mode start; enables jitter-free sampling synchronized to external timer or PLL. |
| 3 (CLK) | External clock input / oscillator enable | Tie to VSS to activate internal 2 MHz clock; allows system-level clock domain alignment without external crystal. |
| 4 (SSTRB) | Active-low serial frame strobe | Three-state open-collector output; must be pulled up externally (4.7 kΩ); defines 14-bit serial word boundary. |
| 5 (SCLK) | Gated serial clock output | Open-drain output requiring 2 kΩ pull-up; clock edges drive SDATA valid transitions; frequency derived from ADC core clock. |
| 6 (SDATA) | Serial data output | Three-state open-collector output; data valid on falling SCLK edge when SSTRB low; LSB-first transmission confirmed. |
| 8 (DGND) | Digital ground return | Separate from AGND; must be connected to system digital plane with low-inductance path to minimize digital switching noise coupling. |
| 9 & 16 (VDD) | +5 V analog power supply | Dual VDD pins (9 and 16) require direct tie together and local 0.1 μF + 10 μF decoupling to AGND; ensures stable reference and comparator operation. |
| 11 (CREF) | Internal reference decoupling node | Connect 10 nF capacitor to AGND here; critical for minimizing reference noise and maintaining 80 dB SNR performance. |
| 12 (AGND) | Analog ground reference | Star-point connection for VIN, REFOUT, CREF, and analog section; must be isolated from DGND except at single-point system ground. |
| 13 (REFOUT) | 3 V reference voltage output | Capable of sourcing 500 μA; max 50 pF capacitive load; use series 200 Ω + parallel 10 μF/0.1 μF for external buffering. |
| 14 (VIN) | Bipolar analog input | ±3 V range into 15 kΩ typical input impedance; accepts dc-coupled or ac-coupled signals; track-and-hold settles in ≤2 μs. |
| 15 (VSS) | −5 V analog power supply | Requires local 0.1 μF + 10 μF decoupling to AGND; negative rail stability directly impacts INL and THD performance. |
Key Features
| Feature | Design Value |
|---|---|
| Complete monolithic ADC | No external clock, reference, or track-and-hold components required - reduces BOM count and layout area in space-constrained DAQ modules. |
| LC2MOS process technology | Enables high-speed, low-power operation with excellent dc accuracy (±1 LSB INL max) and dynamic performance (−86 dB THD) in same die. |
| Self-contained 2 MHz clock | Eliminates crystal oscillator, capacitors, and associated layout sensitivity; simplifies compliance testing and reduces EMI sources. |
| Twos-complement coding | Direct interface to DSPs and microcontrollers with signed arithmetic units; avoids software sign-extension overhead in real-time processing. |
| Buried Zener reference | Factory-trimmed 3.00 V ±10 mV with ±40 ppm/°C drift - stable enough for uncalibrated industrial sensor front-ends operating from −40°C to +85°C. |
Applications
| High-Speed Modem Front-End | Spectrum Analyzer Digitizer |
|---|---|
|
Use Scenario: Digitizing IF signals in QAM/QPSK demodulation chains with 10–20 MHz bandwidth requirements. IC Role / Device Role / Timing Role: ADC sampling stage providing 14-bit resolution and 83 kSPS sustained rate for baseband I/Q reconstruction. Use Value: 80 dB SNR ensures >60 dB carrier-to-noise ratio in 16-QAM systems; serial interface minimizes routing congestion on RF-adjacent PCB layers. |
Use Scenario: Capturing transient spectral events in real-time FFT-based analyzers with ≥40 kHz effective Nyquist bandwidth. IC Role / Device Role / Timing Role: High-fidelity analog capture element synchronizing to sweep generator via CONVST for repeatable spectral snapshots. Use Value: ≤2 μs track-and-hold acquisition enables accurate amplitude measurement of fast-rising spectral peaks; internal reference eliminates external ref drift errors. |
| DSP-Based Servo Control Loop | Voice Recognition Preprocessing |
|
Use Scenario: Sampling motor current and position feedback in closed-loop motion controllers requiring sub-microsecond timing determinism. IC Role / Device Role / Timing Role: Precision analog input conditioner feeding TI C2000 or Analog Devices SHARC processors with deterministic CONVST-triggered sampling. Use Value: 57 ns data access time allows immediate post-conversion processing within tight ISR deadlines; ±1 LSB INL maintains torque linearity across full speed range. |
Use Scenario: Digitizing microphone outputs in embedded voice command systems operating in noisy acoustic environments. IC Role / Device Role / Timing Role: Low-noise front-end ADC capturing 8–12 kHz speech band with minimal harmonic distortion for MFCC feature extraction. Use Value: −86 dB THD prevents spectral leakage that degrades phoneme classification; serial interface eases integration with low-pin-count microcontrollers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 14-bit serial-output ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8320UB | 16-bit resolution, SPI interface, 100 kSPS, external reference required, no internal track-and-hold. | Higher resolution but needs external op-amp driver and reference; better for precision DC measurements than dynamic signal capture. | Select ADS8320UB only if 16-bit ENOB and SPI compatibility outweigh added BOM cost and layout complexity. |
| MAX1166BCAP+ | 14-bit, serial interface, 100 kSPS, internal reference (2.048 V), single +5 V supply, no bipolar input support. | Limited to unipolar 0–VREF input; lacks ±3 V range and buried Zener stability; suited for battery-powered sensor nodes. | Choose MAX1166BCAP+ only for low-voltage, unipolar applications where supply count reduction is critical and bipolar range is unnecessary. |
Compared with AD7872BR-REEL, ADS8320UB offers higher resolution but demands external signal conditioning and reference management, while MAX1166BCAP+ simplifies power design but sacrifices bipolar input capability and reference stability - making AD7872BR-REEL uniquely balanced for industrial DSP interfacing with minimal external components.
Availability
AD7872BR-REEL is available at Aetrix Electronics and suitable for high-speed modems, spectrum analyzers, DSP servo control systems, and voice recognition preprocessors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AD7872BR-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD7872BR-REEL belongs to the AD7871/AD7872 family of complete monolithic sampling ADCs designed specifically for demanding digital signal processing applications where integration, speed, and dynamic fidelity are critical.
FAQ
What is the function of the CONTROL pin on the AD7872BR-REEL?
The CONTROL pin on the AD7872BR-REEL selects serial clock behavior: at 0 V it enables gated SCLK (active only during serial transmission), and at −5 V it enables continuous SCLK output. This setting directly affects timing predictability and bus loading in systems using multiple AD7872BR-REEL devices sharing the same SCLK line. The pin has no effect on conversion timing or data validity - AD7872BR-REEL always outputs 14-bit serial data on SDATA with SSTRB framing.
Does the AD7872BR-REEL support parallel data output?
No, the AD7872BR-REEL supports serial output only via SSTRB, SCLK, and SDATA pins. Unlike the pin-compatible AD7871, the AD7872BR-REEL omits all parallel data bus pins (DB0–DB13) and related control lines (CS, RD, BUSY/INT). This serial-only architecture reduces pin count and PCB routing complexity but requires firmware to manage bit-serial readout - a confirmed design constraint explicitly stated in the AD7872 functional block diagram and pin descriptions.
What is the maximum recommended capacitive load on the REFOUT pin of the AD7872BR-REEL?
The maximum recommended capacitive load on the REFOUT pin of the AD7872BR-REEL is 50 pF for normal operation. Exceeding this value risks instability and degraded SNR performance. If external buffering is needed, Analog Devices specifies a series 200 Ω resistor followed by parallel 10 μF tantalum and 0.1 μF ceramic decoupling - a configuration validated to maintain 80 dB SNR and prevent reference droop during conversion cycles in the AD7872BR-REEL datasheet.
Can the AD7872BR-REEL operate with a single +5 V supply?
No, the AD7872BR-REEL requires dual ±5 V supplies (VDD = +5 V, VSS = −5 V) as specified in Absolute Maximum Ratings and confirmed in all electrical characteristics tables. Operation outside this supply range violates the device's internal biasing scheme and compromises both dc accuracy (e.g., ±12 LSB gain error) and dynamic performance (e.g., SNR drops below 80 dB). The AD7872BR-REEL has no single-supply variant - attempting +5 V only will result in nonfunctional or damaged units.
What is the purpose of the CREF pin on the AD7872BR-REEL?
The CREF pin on the AD7872BR-REEL is the dedicated decoupling node for the internal buried Zener reference. A 10 nF capacitor must be connected between CREF and AGND to suppress high-frequency reference noise and ensure specified 80 dB SNR performance. This capacitor is not optional - datasheet Figure 10 and Theory of Operation section explicitly state that omitting or misplacing the CREF capacitor degrades dynamic specifications and introduces measurable spurious tones in the output spectrum of the AD7872BR-REEL.
AD7872BR-REEL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 83k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- SPI, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- ±5V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 16-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD7872BR-REEL FAQ
1.How can I place an order for AD7872BR-REEL through Aetrix?
Please submit a Request for Quotation (RFQ) for AD7872BR-REEL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD7872BR-REEL reliable?
The price and inventory of AD7872BR-REEL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD7872BR-REEL is usually 5 days.
3.What payment methods are accepted for AD7872BR-REEL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD7872BR-REEL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD7872BR-REEL?
AD7872BR-REEL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD7872BR-REEL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD7872BR-REEL?
For technical support, including AD7872BR-REEL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD7872BR-REEL requirements.
6.How does Aetrix verify that AD7872BR-REEL is sourced from the original manufacturer or authorized distributors?
All AD7872BR-REEL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD7872BR-REEL meets industry standards.
7.What is the process for return or replacement of AD7872BR-REEL?
All AD7872BR-REEL units undergo pre-shipment inspection (PSI). If there is an issue with AD7872BR-REEL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD7872BR-REEL part is unused and in its original packaging.
Return procedure for AD7872BR-REEL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD7872BR-REEL Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

