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Analog Devices Inc. AD7872JRZ
- Part No.:
- AD7872JRZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AD7872JRZ.pdf
- Description:
- IC ADC 14BIT SAR 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,496
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Product details
Overview
AD7872JRZ from Analog Devices is a complete monolithic 14-bit successive approximation analog-to-digital converter (ADC) with integrated track-and-hold amplifier, 3 V buried Zener reference, and serial-only digital interface. It operates from ±5 V supplies, accepts ±3 V bipolar analog inputs, achieves 83 kSPS throughput, delivers 80 dB SNR at 10 kHz, and features 57 ns data access time. It is used in high-speed DSP servo control and spectrum analysis systems requiring precise timing and low-noise sampling.
For engineers reviewing the AD7872JRZ datasheet, AD7872JRZ pinout, AD7872JRZ application, or AD7872JRZ equivalent, this page provides verified technical context, real-world interface constraints, dynamic performance limits under specified conditions, package-specific layout guidance, and validated alternative options for serial-output 14-bit ADC replacement scenarios.
Technical Context
The AD7872JRZ implements a self-contained LC2MOS architecture with an internal laser-trimmed 2 MHz clock - eliminating external timing components unless synchronization to system clocks is required. Its track-and-hold amplifier acquires signals to 14-bit accuracy in ≤2 μs and supports full-power input frequencies up to 41.5 kHz.
All digital outputs (SSTRB, SCLK, SDATA) are three-state, open-drain or pull-up–dependent, requiring external 4.7 kΩ (SSTRB, SDATA) and 2 kΩ (SCLK) resistors. The device uses twos-complement coding, supports only serial data output, and relies on CONVST-triggered conversion initiation - no CS/RD parallel control mode is available.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit - guarantees no missing codes; LSB = 366 µV for ±3 V input range. |
| Throughput Rate | 83 kSPS - maximum sustained sampling rate with internal 2 MHz clock. |
| SNR @ 10 kHz | 80 dB min - defines usable dynamic range for audio and baseband signal digitization. |
| Conversion Time | 10.5 µs max (internal clock) - determines minimum inter-sample interval in time-critical control loops. |
| Analog Input Range | ±3 V - bipolar full-scale range referenced to AGND; requires matched ±5 V supplies. |
| Reference Output | 3.00 V ±10 mV @ +25°C - stable on-chip Zener source; load-limited to 500 µA. |
| Power Dissipation | 50 mW typ - enables low-thermal-impact placement near sensitive analog circuitry. |
| Supply Voltages | ±5 V ±5% - dual-rail operation; VDD and VSS must be independently decoupled. |
Pinout & Package
AD7872JRZ is housed in a 16-pin SOIC package (width: 7.5 mm), RoHS-compliant, with standard JEDEC MS-012AC outline. Pin 1 is CONTROL; pin 16 is VDD (tied internally to pin 9). No NC pins affect routing; CREF requires mandatory 10 nF AGND decoupling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CONTROL) | Serial clock gating control | Selects SCLK behavior: 0 V → gated-off after transmission; −5 V → continuous SCLK output. |
| 2 (CONVST) | Asynchronous conversion trigger | Rising edge initiates track→hold transition; no dependency on CLK edge alignment. |
| 3 (CLK) | External clock input / oscillator enable | Tie to VSS to activate internal 2 MHz clock; apply TTL-compatible signal for external timing. |
| 4 (SSTRB) | Active-low serial framing pulse | Three-state open-drain output; requires 4.7 kΩ pull-up; defines serial word boundaries. |
| 5 (SCLK) | Gated serial clock output | Open-drain; requires 2 kΩ pull-up; data valid on falling edge when SSTRB is low. |
| 6 (SDATA) | Serial data output | Three-state open-drain; requires 4.7 kΩ pull-up; MSB-first, twos-complement format. |
| 8 (DGND) | Digital ground return | Must be isolated from AGND except at single-point star ground; avoids digital noise coupling. |
| 9 & 16 (VDD) | +5 V analog supply | Pins 9 and 16 are internally connected; both require local 0.1 µF ceramic + 10 µF tantalum decoupling. |
| 11 (CREF) | Reference decoupling node | Connect 10 nF capacitor directly to AGND; critical for minimizing reference noise and INL drift. |
| 12 (AGND) | Analog ground reference | Return for VIN, REFOUT, CREF; must be physically separated from DGND traces and planes. |
| 13 (REFOUT) | 3 V reference output | Capable of sourcing 500 µA; max 50 pF capacitive load; external use requires RC filter (200 Ω + 10 µF||0.1 µF). |
| 14 (VIN) | Bipolar analog input | ±3 V range into 15 kΩ typical impedance; bandwidth >500 kHz; track-and-hold acquisition ≤2 µs. |
| 15 (VSS) | −5 V analog supply | Requires independent decoupling; not shared with digital logic grounds or supplies. |
Key Features
| Feature | Design Value |
|---|---|
| Complete monolithic ADC | No external DAC, reference, or track-and-hold required - reduces BOM count and layout area by ≥4 components. |
| Integrated 3 V buried Zener reference | Factory-trimmed to ±10 mV over temperature; eliminates need for precision external reference ICs or trimming. |
| Self-contained internal clock | 2 MHz laser-trimmed oscillator removes crystal, capacitors, and clock buffer - simplifies timing design and EMI control. |
| Twos-complement serial output | Direct interface to DSP serial ports (e.g., TMS320Cxx, ADSP-21xx) without format conversion logic or glue logic. |
| Low power consumption | 50 mW typical at 83 kSPS - enables battery-operated or thermally constrained instrumentation designs. |
| Bipolar input support | ±3 V range with internal offset handling - avoids external level-shifting op amps in sensor front-ends. |
Applications
| Digital Signal Processing (DSP) Systems | High-Speed Modem Front-Ends |
|---|---|
|
Use Scenario: Real-time acquisition of baseband I/Q signals in software-defined radio receivers operating up to 41.5 kHz full-power bandwidth. IC Role / Device Role / Timing Role: ADC core performing synchronized sampling triggered by FPGA-controlled CONVST pulses; serial output fed directly to DSP serial port. Use Value: 80 dB SNR ensures clean spectral representation for FFT-based channel estimation; 57 ns access time enables tight loop timing in adaptive equalizers. |
Use Scenario: Digitizing analog line signals in V.34/V.90 modem chipsets where jitter-sensitive symbol recovery demands precise sample timing. IC Role / Device Role / Timing Role: Standalone sampling engine with CONVST driven by PLL-synchronized timer; serial output aligned to DSP frame sync. Use Value: Internal clock eliminates external crystal-induced phase noise; ±1 LSB INL maintains symbol decision accuracy across temperature. |
| Spectrum Analysis Instruments | DSP-Based Servo Control Loops |
|
Use Scenario: High-fidelity acquisition stage in portable spectrum analyzers capturing 0–20 kHz audio and vibration spectra with minimal harmonic distortion. IC Role / Device Role / Timing Role: Primary ADC in analog front-end; REFOUT powers external anti-aliasing filter op amps; CREF decoupling ensures THD < −85 dB. Use Value: 86 dB THD and −86 dB spurious noise floor preserve weak signal visibility in FFT bins; 14-bit resolution resolves 0.006% amplitude steps. |
Use Scenario: Closed-loop position feedback in industrial motion controllers where 14-bit encoder interpolation or analog resolver digitization is required. IC Role / Device Role / Timing Role: Resolver-to-digital converter interface; CONVST synchronized to PWM carrier edge to reject switching noise. Use Value: Track-and-hold acquisition ≤2 µs rejects high-frequency EMI from motor drives; ±12 LSB gain error spec ensures repeatable torque calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial-output 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8320UB | 16-bit resolution, SPI interface, 100 kSPS, external reference required, no internal track-and-hold. | Higher resolution but needs external op amp driver and reference; better for precision DC measurements than AC-coupled DSP. | Choose ADS8320UB when 16-bit static accuracy outweighs integration benefits and system can accommodate external support components. |
| MAX1166BCAP+ | 14-bit, serial SPI, 100 kSPS, internal reference (2.048 V), single +5 V supply, no bipolar input support. | Limited to unipolar 0–VREF input; lacks ±5 V dual supply and ±3 V bipolar range; lower SNR (76 dB). | Choose MAX1166BCAP+ only for cost-sensitive unipolar applications where ±3 V input and 80 dB SNR are not required. |
Compared with AD7872JRZ, ADS8320UB offers higher resolution but increases system complexity with external analog support, while MAX1166BCAP+ reduces supply count and cost but sacrifices bipolar input capability, SNR, and thermal stability - making AD7872JRZ optimal for integrated, low-noise, bipolar DSP acquisition.
Availability
AD7872JRZ is available at Aetrix Electronics and suitable for digital signal processing systems, high-speed modem designs, spectrum analysis instruments, and DSP servo control loops requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for AD7872JRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.
The AD7872JRZ belongs to the AD7871/AD7872 family of fast, complete 14-bit sampling ADCs designed specifically for demanding DSP, communications, and instrumentation applications requiring integrated timing, reference, and bipolar signal handling.
FAQ
What is the maximum input frequency the AD7872JRZ can accurately digitize?
The AD7872JRZ supports full-power analog input signals up to 41.5 kHz while maintaining 14-bit accuracy and specified SNR/THD performance. This limit arises from the track-and-hold amplifier's 500 kHz 0.1 dB bandwidth and acquisition time ≤2 µs. For signals above 41.5 kHz, amplitude attenuation and harmonic distortion increase beyond datasheet specifications - anti-aliasing filtering is mandatory for Nyquist-compliant sampling.
Does the AD7872JRZ require external clock components to operate?
No - the AD7872JRZ includes a self-contained, laser-trimmed 2 MHz internal oscillator. Tying the CLK pin to VSS activates this clock, eliminating crystals, capacitors, or clock buffers. An external TTL-compatible clock may be applied to CLK only if system-level synchronization is needed; in that case, the internal oscillator is disabled automatically.
Can the AD7872JRZ interface directly with a microcontroller's SPI port?
Yes, but with hardware adaptation: AD7872JRZ outputs serial data (SDATA) on the falling edge of SCLK with framing via active-low SSTRB - matching SPI Mode 1 (CPOL=0, CPHA=1) timing. However, SCLK is open-drain and requires a 2 kΩ pull-up, and SSTRB is also open-drain (4.7 kΩ pull-up), so direct connection to standard SPI master GPIOs is possible only if those pins support open-drain drive and external pull-ups are added.
What is the purpose of the CREF pin on the AD7872JRZ, and how must it be connected?
The CREF pin is the dedicated decoupling node for the internal 3 V buried Zener reference. It must be connected to AGND via a 10 nF ceramic capacitor placed as close as possible to the pin. This capacitor stabilizes the reference against high-frequency noise and prevents degradation of INL and SNR. Omitting or misplacing this capacitor causes measurable increase in integral nonlinearity and spurious content in the output spectrum.
Is the AD7872JRZ pin-compatible with the AD7871 series?
No - the AD7872JRZ uses a 16-pin SOIC package with serial-only interface (SSTRB/SCLK/SDATA), while the AD7871 uses a 28-pin package with parallel/byte/serial selectable outputs (DB0–DB13, CS, RD, BUSY/INT). Their pin counts, functions, and physical layouts are incompatible; PCB redesign and firmware changes are required for substitution.
AD7872JRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 83k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- SPI, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- ±5V
- Voltage - Supply, Digital:
- ±5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD7872JRZ FAQ
1.How can I place an order for AD7872JRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD7872JRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD7872JRZ reliable?
The price and inventory of AD7872JRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD7872JRZ is usually 5 days.
3.What payment methods are accepted for AD7872JRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD7872JRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD7872JRZ?
AD7872JRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD7872JRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD7872JRZ?
For technical support, including AD7872JRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD7872JRZ requirements.
6.How does Aetrix verify that AD7872JRZ is sourced from the original manufacturer or authorized distributors?
All AD7872JRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD7872JRZ meets industry standards.
7.What is the process for return or replacement of AD7872JRZ?
All AD7872JRZ units undergo pre-shipment inspection (PSI). If there is an issue with AD7872JRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD7872JRZ part is unused and in its original packaging.
Return procedure for AD7872JRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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