Analog Devices Inc. AD7960BCPZ

Overview

AD7960BCPZ from Analog Devices is an 18-bit, 5 MSPS charge redistribution successive approximation register (SAR) analog-to-digital converter with true differential input, ±4.096 V or ±5 V range, 99 dB SNR, and LVDS serial interface. It delivers no missing codes, ±0.8 LSB typical INL, and operates across −40°C to +85°C in high-speed data acquisition systems requiring precision timing and low latency.

For engineers reviewing the AD7960BCPZ datasheet, AD7960BCPZ pinout, AD7960BCPZ application, or AD7960BCPZ equivalent, key selection criteria include throughput vs. power trade-offs (39–64.5 mW), reference configuration options (external 4.096 V/5 V or internal buffered 2.048 V → 4.096 V), LVDS self-clocked vs. echoed clock mode, and true differential input handling for MRI gradient control or spectroscopy front-ends.

Technical Context

The AD7960BCPZ implements a SAR architecture with no pipeline delay-enabling deterministic, zero-latency conversion critical for closed-loop control. Its differential input stage accepts antiphase signals swinging between 0 V and 4.096 V or 0 V and 5 V, referenced to VCM = REF/2, with 70 dB CMRR at 500 kHz.

Conversion is triggered on the rising edge of CNV±, supporting both LVDS and CMOS-level control inputs. Data output uses ANSI-644-compliant LVDS signaling (D±, DCO±) with twos-complement format, configurable for self-clocked (20-bit frame: 0 + header + 18 data bits) or echoed clock (18-bit frame synchronized to CLK±) operation.

Key Specifications

Pinout & Package

AD7960BCPZ is housed in a 32-lead, 5 mm × 5 mm LFCSP (QFN) package with exposed pad (EP) for thermal management. Pin assignments are validated per Analog Devices' Rev. C datasheet (Page 8, Figure 4 and Table 6).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, high-resolution ADC applications.

Compared with AD7961BCPZ, AD7960BCPZ adds 2 bits of resolution and 3.5 dB SNR for demanding medical imaging; compared with AD7982BRUZ, it trades 5 MSPS lower throughput for LVDS noise immunity, integrated reference buffer, and zero-latency operation-critical for real-time control.

Availability

AD7960BCPZ is available at Aetrix Electronics and suitable for digital imaging systems, MRI gradient control subsystems, and high-speed test equipment requiring stable component supply, long-term lifecycle support, and guaranteed lot traceability.

Supply support for AD7960BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD7960BCPZ belongs to Analog Devices' PulSAR® family of high-speed SAR ADCs, designed specifically for applications demanding simultaneous high resolution, high throughput, and low latency-such as medical imaging, scientific instrumentation, and industrial automation.

FAQ

What is the maximum sample rate supported by the AD7960BCPZ?

The AD7960BCPZ supports a maximum throughput rate of 5 MSPS, corresponding to a minimum conversion cycle time of 200 ns. This is achievable in both self-clocked and echoed clock LVDS interface modes, provided the host system meets timing requirements for DCO± or CLK± signal integrity and setup/hold margins.

Does the AD7960BCPZ require an external reference voltage?

The AD7960BCPZ supports multiple reference configurations: it can accept an external 4.096 V or 5 V reference on the REF pin, or a 2.048 V reference on REFIN to enable its internal reference buffer (producing 4.096 V at REF). No external reference is mandatory-the choice depends on system accuracy, noise, and board area constraints.

How does the LVDS interface of the AD7960BCPZ operate in self-clocked mode?

In self-clocked mode (DCO+ grounded), the AD7960BCPZ outputs a 20-bit frame on D±: initial 0 bit, followed by 2-bit header (10), then 18 data bits. The host captures data using the falling edge of DCO± as a synchronous strobe-eliminating need for external clock distribution and reducing skew-related timing errors in the AD7960BCPZ data path.

What is the purpose of the VCM pin on the AD7960BCPZ?

The VCM pin on the AD7960BCPZ provides a buffered output equal to REF/2 (e.g., 2.048 V when REF = 4.096 V), intended to drive the common-mode voltage of external differential input amplifiers. This eliminates the need for external resistive dividers or op-amp buffers, improving matching, reducing noise, and simplifying layout in precision signal chains using the AD7960BCPZ.

Can the AD7960BCPZ be used in systems with only CMOS-level digital interfaces?

Yes-the AD7960BCPZ supports CMOS-level conversion control: grounding CNV− allows CNV+ to function as a CMOS input (1.8 V logic), while maintaining full 5 MSPS throughput. However, the data interface remains LVDS (D±, DCO±); an LVDS-to-CMOS translator or FPGA with LVDS-capable I/O banks is required to receive the serial output stream from the AD7960BCPZ.