Analog Devices Inc. AD80066KRSZRL

Overview

AD80066KRSZRL from Analog Devices is a complete 16-bit CCD/CIS analog signal processor with integrated 4-channel correlated double sampling (CDS), programmable gain amplifiers (PGA), offset DACs, and a 24 MSPS ADC. It supports 4-/3-/2-/1-channel operation, selectable 1.5 V or 3 V p-p input range, ±300 mV offset adjustment, and multiplexed 8-bit digital output. It is used in flatbed document scanners for high-fidelity digitization of optical sensor outputs.

For engineers reviewing the AD80066KRSZRL datasheet, AD80066KRSZRL pinout, AD80066KRSZRL application, or AD80066KRSZRL equivalent, key selection considerations include CDS vs. SHA mode configuration, channel count scalability, 16-bit accuracy at 24 MSPS, and SSOP-28 layout compatibility for imaging front-end designs.

Technical Context

The AD80066KRSZRL implements a fully integrated analog signal chain optimized for linear image sensors: each of its four channels includes an input clamp, CDS amplifier, 9-bit offset DAC, and PGA-multiplexed to a single 16-bit ADC. Its dual-clock CDS architecture (CDSCLK1 for reference level, CDSCLK2 for data level) enables precise noise cancellation in CCD outputs.

It supports configurable operating modes via a 3-wire serial interface: CDS or SHA sampling, 1–4 channel selection, 1.5/3 V input range, 2-byte or single-byte output, and power-down/slow-mode control. The internal bandgap reference and 3 V/5 V digital I/O compatibility simplify system-level integration in scanner and copier platforms.

Key Specifications

Pinout & Package

AD80066KRSZRL is housed in a 28-lead SSOP (Shrink Small Outline Package) with 0.65 mm lead pitch, optimized for surface-mount assembly in space-constrained imaging modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCD/CIS signal processor applications.

Compared with TDC1308IPWPR and AD9945KSTZ, AD80066KRSZRL uniquely combines 16-bit resolution, full 4-channel CDS/SHA configurability, on-chip offset DACs, and SSOP-28 packaging-making it the only single-chip solution for high-fidelity, multi-sensor, thermally constrained scanner designs requiring factory and field calibration.

Availability

AD80066KRSZRL is available at Aetrix Electronics and suitable for flatbed document scanners, film scanners, and digital color copiers requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial imaging OEMs.

Supply support for AD80066KRSZRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD80066KRSZRL belongs to Analog Devices' Imaging Signal Processor product line, designed specifically to replace discrete CDS+PGA+ADC signal chains in professional and consumer document/film scanning equipment.

FAQ

What is the maximum pixel rate supported by AD80066KRSZRL in 4-channel CDS mode?

The AD80066KRSZRL supports a maximum pixel rate of 24 MSPS in 4-channel CDS mode, corresponding to 6 MHz per channel. This is confirmed in Table 1 of the datasheet under "Maximum Conversion Rate" and validated by timing diagrams Figure 3 and Figure 7. The 24 MSPS rate is achievable with fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, and PGA gain = 1. AD80066KRSZRL maintains guaranteed INL and DNL performance at this rate.

Can AD80066KRSZRL be used with contact image sensors (CIS) that do not require correlated double sampling?

Yes, AD80066KRSZRL can be configured for SHA (sample-and-hold) mode by setting Bit D3 high in the configuration register, which disables the CDS amplifiers. In this mode, CDSCLK1 is grounded and CDSCLK2 serves as the sole sampling clock. The datasheet explicitly states this capability in the "General Description" and "4-Channel SHA Mode" sections, confirming suitability for CIS and CMOS sensors. AD80066KRSZRL retains all other features-including per-channel gain/offset-in SHA mode.

What is the function of the OFFSET pin on AD80066KRSZRL?

The OFFSET pin on AD80066KRSZRL serves as both a coarse analog offset adjustment node and a decoupling terminal. When a voltage is applied, it is subtracted from all four analog inputs (VINA–VIND) in the first amplifier stage. It also provides a low-impedance path for bias current return. The datasheet specifies ±300 mV programmable offset range via internal 9-bit DACs, while the OFFSET pin itself accepts external bias voltages for additional calibration flexibility. AD80066KRSZRL's functional block diagram and Pin Function Descriptions confirm this dual role.

Does AD80066KRSZRL support single-supply operation for both analog and digital domains?

AD80066KRSZRL requires separate analog and digital supplies: AVDD = 4.5–5.25 V (analog core) and DRVDD = 3.0–5.25 V (digital output drivers). While DRVDD can be set to 5 V to match AVDD, the datasheet specifies distinct pin assignments (Pin 1/18 AVDD, Pin 5 DRVDD) and independent ground returns (AVSS vs. DRVSS) to prevent digital switching noise from corrupting analog performance. Therefore, AD80066KRSZRL does not support true single-supply operation-it mandates split-rail supply design per the Absolute Maximum Ratings and Power Supplies tables.

How is the 16-bit output formatted on the D[0:7] bus of AD80066KRSZRL?

The AD80066KRSZRL delivers its 16-bit output in multiplexed byte-wide format: the most significant byte (DB15–DB8) appears on D[7:0] during the ADCCLK rising edge, and the least significant byte (DB7–DB0) appears on the falling edge. This is enabled by default (Bit D4 = 0 in Configuration Register). An optional single-byte mode (Bit D4 = 1) outputs DB15–DB8 only, reducing interface complexity. Both formats are detailed in Figures 9–10 and the "Digital Output" section of the datasheet. AD80066KRSZRL's timing diagrams validate the 3-cycle pipeline latency for either mode.