Analog Devices Inc. AD802-155KR

Overview

AD802-155KR from Analog Devices is a second-order phase-locked loop (PLL) clock recovery and data retiming IC designed for 155.52 Mbps STS-3/STM-1 telecommunications applications. It accepts NRZ data without preamble, delivers differential recovered clock and retimed data outputs, and operates with ±5.2 V or +5 V supply across 0°C to +70°C. Its 0.08% fractional loop bandwidth and 0.08 dB jitter peaking enable stable lock on scrambled data within 4 × 10⁵ bit periods.

For engineers reviewing the AD802-155KR datasheet, AD802-155KR pinout, AD802-155KR application, or AD802-155KR equivalent, this page provides verified technical context, real-world timing performance metrics, package-specific layout guidance, and validated alternative options for telecom clock recovery designs requiring ECL-compatible signal integrity and jitter tolerance per CCITT G.958 STM-1 Type A mask.

Technical Context

The AD802-155KR implements a dual-loop PLL architecture: a frequency acquisition loop first locks input data rate, then a phase-lock loop tracks phase variations. Its patented phase detector eliminates pattern jitter, while the integrated VCO-trimmed to ±20% center frequency accuracy-removes external tuning components.

Loop damping is set by an external capacitor (e.g., 0.22 µF for ζ = 10), directly controlling jitter peaking (0.02–2 dB) and acquisition time (1.5×10⁴–1.4×10⁶ bit periods). Jitter bandwidth is fixed at 0.08% of 155.52 MHz (≈130 kHz), ensuring 3 dB attenuation of sinusoidal input jitter at that frequency.

Key Specifications

Pinout & Package

AD802-155KR is housed in a 20-pin plastic SOIC package (R-20), measuring 0.394–0.419 inches wide (10.00–10.65 mm), with 0.050-inch lead pitch (1.27 mm). Thermal resistance is θJA = 75°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock recovery applications.

Compared with AD802-155BR, the AD802-155KR trades wider temperature tolerance for lower cost and tighter qualification in commercial telecom infrastructure; versus ICS8430M-01LFT, it offers true preamble-free lock and ECL-level robustness at the expense of higher supply current and negative voltage support.

Availability

AD802-155KR is available at Aetrix Electronics and suitable for SONET/SDH line card timing, OC-3/STM-1 data retiming, and telecom test equipment requiring stable component supply with consistent parametric performance across production lots.

Supply support for AD802-155KR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The AD800/AD802 product line was engineered specifically for telecom clock recovery in NRZ-based systems, targeting DS-3, STS-1, and STS-3/STM-1 bit rates with zero-preamble operation and jitter performance compliant to CCITT G.958.

FAQ

What is the operating temperature range for the AD802-155KR?

The AD802-155KR is specified for operation from 0°C to +70°C (K-grade). This commercial temperature range aligns with indoor telecom infrastructure applications such as central office line cards and enterprise SDH multiplexers. Unlike the AD802-155BR variant, the AD802-155KR does not support –40°C startup or sustained operation, making thermal derating unnecessary in climate-controlled environments.

Does the AD802-155KR require an external crystal or VCXO?

No, the AD802-155KR does not require an external crystal or VCXO. Its integrated, factory-trimmed VCO provides autonomous clock recovery from NRZ data alone. The device achieves frequency lock via its internal frequency detector and phase detector, eliminating dependency on external timing references - a key advantage over conventional PLL-based CDRs.

How is loop damping configured on the AD802-155KR?

Loop damping on the AD802-155KR is set by a single external ceramic capacitor connected between pins CF1 and CF2. For example, a 0.22 µF capacitor yields ζ = 10 (low jitter peaking, slower acquisition), while 2.2 nF gives ζ = 1 (fastest acquisition, 2 dB peaking). Damping factor directly scales with √(f_DATA × C_D), enabling precise trade-off control in the final design.

What is the significance of the FRAC output on the AD802-155KR?

The FRAC (Frequency Acquisition) output on the AD802-155KR is a differential signal that pulses during cycle slips between input data and VCO frequency. It asserts only during frequency acquisition and ceases once frequency lock is achieved - providing a hardware-ready indicator for downstream logic to enable retimed data. Valid AD802-155KR output is guaranteed 2,000 bit periods after the last FRAC pulse.

Can the AD802-155KR operate from a +5 V supply?

Yes, the AD802-155KR supports single-supply operation from either +5 V (with appropriate logic level translation) or –5.2 V (native ECL mode). When using +5 V, VCC is tied to +5 V and VEE to ground; all I/O becomes PECL-compatible. The device maintains full specification compliance-including jitter, skew, and acquisition time-in both configurations, as confirmed in the AD800/AD802 Rev. B datasheet.