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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. AD805BN

Name: AD805BN
Brand: Analog Devices Inc.
SKU: AD805BN
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD805BN

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 20-DIP (0.300", 7.62mm)

Datasheet:: AD805BN.pdf

Description:: CLOCK DRIVER, 805 SERIES

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD805BN from Analog Devices is a data retiming phase-locked loop IC designed for clock recovery and NRZ data retiming at 155.52 Mbps in STM-1/STS-3 telecom systems. It operates with an external VCXO, delivers 0.6° rms output jitter, supports ±50 ppm tracking range, and functions across –40°C to +85°C in regenerative repeater applications.

For engineers reviewing the AD805BN datasheet, AD805BN pinout, AD805BN application, or AD805BN equivalent, this page provides verified technical context, jitter tolerance/transfer performance per CCITT G.958 Type A/B, static phase error (7–33°), acquisition time (30–44 bit periods), and VCXO control interface details critical for telecom clock regeneration design.

Technical Context

The AD805BN implements a dual-loop architecture: a high-speed internal delay-locked loop using an on-chip voltage-controlled phase shifter (VCPS) with ≥2 UI range and ~3 MHz bandwidth handles wideband jitter accommodation, while an external VCXO-based frequency control loop tracks low-frequency jitter components. Both loops share a common control voltage path.

This architecture eliminates jitter peaking by placing the stabilizing zero in the feedback path (within the VCPS), resulting in a closed-loop jitter transfer function with no zero-unlike conventional second-order PLLs. The circuit meets CCITT G.958 STM-1 Type A jitter tolerance and Type B jitter transfer requirements, including 30 kHz corner frequency and <0.12 dB peaking.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Data Rate	155.52 Mbps - precisely matches STM-1/STS-3 telecom standard; enables direct integration into SONET/SDH line cards.
Tracking Range	±50 ppm - defines maximum input data rate deviation the circuit maintains lock without loss of synchronization.
Output Jitter	0.6° rms - low phase noise directly attributable to VCXO stability; ensures minimal timing uncertainty in retimed data.
Jitter Tolerance (f = 650 kHz)	0.84–1.4 UI p-p - quantifies high-frequency jitter rejection capability critical for optical line system interworking.
Acquisition Time	30–44 bit periods - ultra-fast lock enables rapid resynchronization after signal interruption or cold start.
Static Phase Error	7–33° - steady-state sampling offset between recovered clock edge and optimal data sampling point.
Recovered Clock Skew (TRCS)	0.2–1.1 ns - tight timing alignment between CLKOUT rising edge and DATAOUT edge ensures deterministic setup/hold margins.

Pinout & Package

AD805BN is housed in a 20-pin plastic DIP (package option N-20) with separate analog and digital substrate and power domains for noise isolation. Pin assignments are validated per Analog Devices' official pin configuration diagram (Rev. 0).

Pin/Terminal	Circuit Role	Design Meaning
1, 2	Differential Retimed Data Output	Provides ECL-compatible retimed NRZ data; requires 50 Ω termination to VEE for signal integrity.
4, 5	Differential Recovered Clock Output	Delivers low-jitter 155.52 MHz clock; duty cycle distortion limited to ±0.5% for precise timing distribution.
12	VCXO Control Voltage Output	Sinks up to 90 mA; drives external VCXO with 0.8–1.3 V logic-high and –1.15 to –0.8 V logic-low levels.
16, 17	Differential Clock Input	Accepts ECL-level reference clock during VCXO calibration or test modes; not used in normal data retiming operation.
19, 20	Differential Data Input	10 KH ECL-compatible NRZ data input; accepts signals down to 20 mV amplitude with negligible BER degradation.
7, 15, 14, 8, 3	Digital VEE / Ground	Multiple dedicated digital ground pins minimize return-path inductance and reduce crosstalk in high-speed ECL interfaces.
9, 13	Analog VEE / Ground	Isolated analog ground connections preserve phase detector and loop filter accuracy against digital switching noise.
6, 10, 18	Analog/Digital Substrate	Must be tied to respective AVEE or VEE pins per datasheet layout guidelines to prevent latch-up and ensure jitter performance.

Key Features

Feature	Design Value
No jitter peaking	Zero placed in VCPS feedback path eliminates closed-loop zero → avoids hazardous jitter accumulation in cascade regenerators.
Wideband jitter tolerance	3 MHz internal loop bandwidth enables >2 UI p-p tolerance up to 1 MHz - exceeds CCITT G.958 Type A mask.
Fast acquisition	Locks within 30–44 bit periods - 100× faster than typical second-order PLLs due to VCXO stability + VCPS servo action.
Pattern jitter elimination	Patented phase detector suppresses pattern-dependent jitter - essential for long PRBS sequences in telecom testing.
Single-supply ECL operation	Supports –5.2 V or +5 V supply - simplifies power delivery in legacy ECL backplanes and mixed-signal telecom modules.

Applications

SONET/SDH Regenerator	Optical Line System Interworking
Use Scenario: Receiving degraded 155.52 Mbps STM-1 optical signal with accumulated jitter from upstream fiber spans and passive filters. IC Role / Device Role / Timing Role: Performs clock recovery and data retiming to regenerate clean data and clock outputs compliant with CCITT G.958 Type A/B specifications. Use Value: Enables interoperability between active PLL-based and passive SAW/dielectric resonator-based regenerators by meeting both wideband jitter tolerance and narrowband jitter transfer masks.	Use Scenario: Bridging legacy optical equipment using different jitter-handling technologies (e.g., SAW-filter-based vs. VCXO-based systems). IC Role / Device Role / Timing Role: Acts as a jitter-cleansing stage that absorbs interworking limitations caused by mismatched jitter transfer characteristics. Use Value: Eliminates need for costly system-level redesign by providing simultaneous Type A jitter tolerance and Type B jitter transfer compliance in one IC.
VCXO-Based Clock Recovery Module	SAW Filter-Assisted Data Retiming
Use Scenario: Building compact, low-power 155.52 MHz clock recovery circuits using commercial off-the-shelf VCXOs (e.g., Vectron C0-434Y or AT&T 157-Type). IC Role / Device Role / Timing Role: Provides full PLL functionality except VCO - leverages external VCXO for superior frequency stability and low phase noise. Use Value: Reduces bill-of-materials cost and board space versus monolithic PLLs while achieving <0.6° rms output jitter via high-Q crystal reference.	Use Scenario: Implementing clock recovery in cost-sensitive telecom edge devices where SAW filters replace VCXOs for lower cost and size. IC Role / Device Role / Timing Role: Replaces discrete D-flip-flop + analog phase shifter with integrated data retiming loop that servos input data phase to SAW-derived clock. Use Value: Removes SAW-to-phase-shifter matching requirement, enabling robust operation across temperature and voltage variations without manual calibration.

SONET/SDH Regenerator

Optical Line System Interworking

Use Scenario: Receiving degraded 155.52 Mbps STM-1 optical signal with accumulated jitter from upstream fiber spans and passive filters.

IC Role / Device Role / Timing Role: Performs clock recovery and data retiming to regenerate clean data and clock outputs compliant with CCITT G.958 Type A/B specifications.

Use Value: Enables interoperability between active PLL-based and passive SAW/dielectric resonator-based regenerators by meeting both wideband jitter tolerance and narrowband jitter transfer masks.

Use Scenario: Bridging legacy optical equipment using different jitter-handling technologies (e.g., SAW-filter-based vs. VCXO-based systems).

IC Role / Device Role / Timing Role: Acts as a jitter-cleansing stage that absorbs interworking limitations caused by mismatched jitter transfer characteristics.

Use Value: Eliminates need for costly system-level redesign by providing simultaneous Type A jitter tolerance and Type B jitter transfer compliance in one IC.

VCXO-Based Clock Recovery Module

SAW Filter-Assisted Data Retiming

Use Scenario: Building compact, low-power 155.52 MHz clock recovery circuits using commercial off-the-shelf VCXOs (e.g., Vectron C0-434Y or AT&T 157-Type).

IC Role / Device Role / Timing Role: Provides full PLL functionality except VCO - leverages external VCXO for superior frequency stability and low phase noise.

Use Value: Reduces bill-of-materials cost and board space versus monolithic PLLs while achieving <0.6° rms output jitter via high-Q crystal reference.

Use Scenario: Implementing clock recovery in cost-sensitive telecom edge devices where SAW filters replace VCXOs for lower cost and size.

IC Role / Device Role / Timing Role: Replaces discrete D-flip-flop + analog phase shifter with integrated data retiming loop that servos input data phase to SAW-derived clock.

Use Value: Removes SAW-to-phase-shifter matching requirement, enabling robust operation across temperature and voltage variations without manual calibration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock recovery and data retiming applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADN2812	Monolithic 155 Mbps CDR with integrated VCO; no external VCXO required; higher power (550 mW); supports 1.25 Gbps upgrade path.	Used in newer designs where board space and supply count are constrained; lacks AD805BN's VCXO flexibility and ultra-low jitter floor.	Select ADN2812 when migrating to integrated solutions and accepting trade-offs in jitter performance and external component count.
ICS87201	155/622 Mbps dual-rate CDR; uses external VCXO but requires separate loop filter; jitter transfer bandwidth fixed at 12 kHz vs. AD805BN's 10 kHz.	Deployed in multi-rate line cards needing backward compatibility; does not meet CCITT G.958 Type A mask below 300 Hz.	Choose ICS87201 only if dual-rate support is mandatory and sub-300 Hz jitter tolerance is not required.

Compared with ADN2812 and ICS87201, the AD805BN uniquely delivers fundamentally no jitter peaking, fastest acquisition (<44 bit periods), and lowest output jitter (0.6° rms) when paired with high-stability VCXOs - making it optimal for legacy STM-1 regenerator upgrades demanding strict CCITT G.958 compliance.

Availability

AD805BN is available at Aetrix Electronics and suitable for SONET regenerators, optical line system interworking modules, and VCXO-based clock recovery subsystems requiring stable component supply and long-term lifecycle support.

Supply support for AD805BN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The AD805BN belongs to Analog Devices' clock recovery and data retiming (CDR) product line, engineered specifically for telecom infrastructure applications requiring CCITT G.958-compliant jitter performance in STM-1/STS-3 systems.

FAQ

What is the primary function of the AD805BN in telecom systems?

The AD805BN is a dedicated data retiming phase-locked loop IC that recovers a clean 155.52 MHz clock and retimes NRZ data streams in STM-1/STS-3 optical transmission systems. Its core function is to eliminate accumulated jitter from degraded input signals, enabling reliable regeneration per CCITT G.958 standards. The AD805BN achieves this by coordinating an external VCXO with its internal voltage-controlled phase shifter and phase detector - a capability central to its role in regenerative repeaters and line interface units.

Does the AD805BN require an external VCXO to operate?

Yes, the AD805BN requires an external voltage-controlled crystal oscillator (VCXO) to perform clock recovery and data retiming. It does not contain an integrated VCO. The AD805BN generates a control voltage (pin 12) that tunes the VCXO's output frequency to match the incoming data rate. Verified compatible VCXOs include the Vectron C0-434Y and AT&T 157-Type, both specified for 155.52 MHz center frequency, ±50 ppm tuning range, and positive monotonic transfer function. Without this external VCXO, the AD805BN cannot establish or maintain lock.

How does the AD805BN achieve "fundamentally no jitter peaking"?

The AD805BN eliminates jitter peaking by implementing the loop-stabilizing zero inside the feedback path of its on-chip voltage-controlled phase shifter (VCPS), rather than in the forward path like conventional second-order PLLs. This architectural choice ensures the zero does not appear in the closed-loop jitter transfer function - a key distinction confirmed in the AD805BN datasheet's THEORY OF OPERATION section. As a result, the AD805BN exhibits flat jitter gain (<0.12 dB peaking) across its bandwidth, preventing dangerous jitter accumulation in cascaded regenerator chains - a critical advantage over traditional PLLs where peaking degrades system-level jitter budgets.

What are the power supply requirements for the AD805BN?

The AD805BN supports single-supply operation at either –5.2 V (VEE) or +5 V (VCC), with absolute maximum ratings of –6 V and +6 V respectively. At –5.2 V, it draws 70–95 mA (typ. 90 mA), consuming ~375 mW. The device mandates separate analog and digital ground planes, decoupling capacitors (10 µF tantalum + 0.1 µF ceramic per supply pin), and individual VEE connections to all differential I/O terminations to maintain jitter performance. These requirements are strictly defined in the AD805BN datasheet's "USING THE AD805" section and must be followed to achieve specified 0.6° rms output jitter and CCITT G.958 compliance.

Can the AD805BN be used with SAW filters instead of a VCXO?

Yes, the AD805BN can be used with a 155.52 MHz surface acoustic wave (SAW) filter for clock recovery and data retiming, as documented in the "APPLICATIONS" section of the AD805BN datasheet. In this configuration, the SAW filter generates a coarse clock, and the AD805BN's internal data retiming loop - comprising its phase detector, loop filter, and voltage-controlled phase shifter - actively servos the input data phase to align with the SAW-derived clock. This replaces discrete D-flip-flop and analog phase shifter implementations, eliminating matching sensitivity and improving temperature stability. However, overall jitter performance becomes dependent on the SAW filter's Q-factor and phase linearity, not the AD805BN alone.

AD805BN Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 20-DIP (0.300", 7.62mm)

Packaging:: Bulk

Product Status:: Active

Programmable:: -

Type:: Phase Lock Loop (PLL)

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: 1:1

Differential - Input:Output:: No/No

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Through Hole

Grade:: -

Qualification:: -

Supplier Device Package:: 20-DIP

AD805BN FAQ

1.How can I place an order for AD805BN through Aetrix?

Please submit a Request for Quotation (RFQ) for AD805BN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD805BN reliable?

The price and inventory of AD805BN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD805BN is usually 5 days.

3.What payment methods are accepted for AD805BN?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD805BN transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD805BN?

AD805BN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD805BN order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD805BN?

For technical support, including AD805BN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD805BN requirements.

6.How does Aetrix verify that AD805BN is sourced from the original manufacturer or authorized distributors?

All AD805BN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD805BN meets industry standards.

7.What is the process for return or replacement of AD805BN?

All AD805BN units undergo pre-shipment inspection (PSI). If there is an issue with AD805BN, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD805BN part is unused and in its original packaging.

Return procedure for AD805BN:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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