Analog Devices Inc. AD809BRZ

Overview

AD809BRZ from Analog Devices is a 155.52 MHz frequency synthesizer IC that generates ECL/PECL-compatible clock outputs from 19.44 MHz or 9.72 MHz reference inputs. It integrates a low-jitter VCO, phase-frequency detector, loop filter, and input multiplexer in a single 16-pin SOIC package, enabling bit-clock synthesis for SONET/SDH optical line cards.

For engineers reviewing the AD809BRZ datasheet, AD809BRZ pinout, AD809BRZ application, or AD809BRZ equivalent, key selection criteria include its 2.0° RMS output jitter, ±5.2 V or +5 V single-supply operation, 10 kHz ECL/PECL/TTL/CMOS input compatibility, and guaranteed low-drift behavior during input loss.

Technical Context

The AD809BRZ implements a second-order PLL with auto-selecting ×8 or ×16 integer frequency multiplication, supporting both differential PECL (Pins 12/13) and single-ended TTL/CMOS (Pin 10) reference inputs via an internal MUX controlled by Pin 15. Its VCO operates without external tuning components.

Loop dynamics are externally adjustable using two damping capacitors (Pins 7/8), with 22 nF yielding ζ = 10 and 5.6 nF yielding ζ = 5. The device delivers complementary 155.52 MHz PECL outputs (Pins 4/5) with 1.1–1.5 ns rise/fall times and 46–62% symmetry across temperature and supply conditions.

Key Specifications

Pinout & Package

AD809BRZ is housed in a 16-pin narrow-body SOIC (R-16A) package measuring 0.394" × 0.157" (10.0 mm × 4.0 mm), with standard 0.050" lead pitch and gull-wing leads. Thermal resistance θ_JA = 110°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Compared with ICS8430M-01LFT and Si5338A-A-GM, the AD809BRZ offers plug-and-play 155.52 MHz synthesis with zero external components and lowest system-level BOM cost for dedicated SONET/SDH applications.

Availability

AD809BRZ is available at Aetrix Electronics and suitable for SONET line cards, SDH re-timing modules, fiber-in-the-loop terminals, and optical transport switches requiring stable component supply across extended temperature and long product lifecycles.

Supply support for AD809BRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and RF ICs for precision signal processing.

The AD809BRZ belongs to Analog Devices' timing and clock generation product line, engineered specifically for telecom infrastructure applications demanding low-jitter, high-reliability frequency synthesis at SONET/SDH line rates.

FAQ

What is the primary function of the AD809BRZ in telecom timing systems?

The AD809BRZ functions as a fixed-ratio frequency synthesizer generating a precise 155.52 MHz PECL output clock from either a 19.44 MHz or 9.72 MHz reference input. In telecom systems, it serves as the bit-clock source for SONET OC-3 and SDH STM-1 optical interfaces, ensuring synchronization across line cards and minimizing jitter accumulation in multi-stage clock trees. Its design guarantees stable operation across –40°C to +85°C, making AD809BRZ suitable for carrier-grade equipment.

Does the AD809BRZ require external loop filter components?

No, the AD809BRZ integrates all critical PLL components including the phase-frequency detector, charge pump, and VCO, eliminating the need for external resistors or inductors. Only two external ceramic capacitors (CF1 and CF2 on Pins 7 and 8) are required to set loop damping - typically 22 nF each for ζ = 10. This integration reduces bill-of-materials count and PCB footprint, distinguishing AD809BRZ from synthesizers requiring full external loop filters.

How does the input multiplexer (MUX) on Pin 15 operate in the AD809BRZ?

The MUX on Pin 15 selects between two reference sources: TTL/CMOSIN (Pin 10) when MUX = logic low, or differential PECLIN/PECLINN (Pins 12/13) when MUX = logic high. This enables dual-mode operation - local crystal reference for normal operation and recovered data clock for loop-timed applications. The AD809BRZ automatically detects input type based on common-mode voltage at Pins 12/13, allowing robust switching without external level-shifting circuitry.

What happens to the AD809BRZ output if the reference input signal is lost?

When the reference input is lost, the AD809BRZ design guarantees the output frequency drifts low by approximately 20%, rather than unlocking unpredictably or oscillating erratically. This fail-safe behavior prevents downstream PLLs from losing lock simultaneously and supports graceful degradation in redundant timing architectures. For example, a 155.52 MHz output will drop to ~124 MHz, remaining within detectable range for monitoring circuits - a defined characteristic of AD809BRZ, not a failure mode.

Can the AD809BRZ be powered from a +3.3 V supply?

No, the AD809BRZ is specified only for +5 V or –5.2 V single-supply operation, with absolute maximum supply voltage of +12 V and operating range of +4.5 V to +5.5 V. It lacks internal regulation for lower voltages, and applying +3.3 V will result in improper biasing of the PECL output stage and failure to meet jitter or output swing specifications. Designs requiring +3.3 V compatibility must use alternative synthesizers - the AD809BRZ requires strict adherence to its +5 V supply condition.