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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. AD809BRZ-REEL

Name: AD809BRZ-REEL
Brand: Analog Devices Inc.
SKU: AD809BRZ-REEL
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD809BRZ-REEL

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: AD809BRZ-REEL.pdf

Description:: IC CLK/FREQ SYNTH 16SOIC

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Product details

Overview

AD809BRZ-REEL from Analog Devices is a 155.52 MHz frequency synthesizer IC that generates ECL/PECL-compatible clock outputs from 19.44 MHz or 9.72 MHz reference inputs. It integrates a low-jitter VCO, phase-frequency detector, loop filter, and input multiplexer in a single 16-pin SOIC package, and is used as a transmit bit clock generator in SONET/SDH optical line cards.

For engineers reviewing the AD809BRZ-REEL datasheet, AD809BRZ-REEL pinout, AD809BRZ-REEL application, or AD809BRZ-REEL equivalent, key selection criteria include its ×8/×16 synthesis capability, 2.0° RMS output jitter, ±40°C to +85°C operating range, single +5 V supply operation, and PECL/TTL/CMOS input compatibility.

Technical Context

The AD809BRZ-REEL implements a second-order PLL architecture with auto-selecting input multiplexer (TTL/CMOSIN vs. CLKIN/CLKINN), on-chip VCO, and configurable loop damping via external capacitors CF1 and CF2. Its PFD drives a charge pump into an RC loop filter, enabling stable lock to either 19.44 MHz (×8) or 9.72 MHz (×16) references.

Output stage delivers complementary 155.52 MHz PECL signals (CLKOUT/CLKOUTN) with 1.1–1.5 ns rise/fall times, 46–62% symmetry, and guaranteed low-phase-skew timing-falling edge at CLKOUTN leads rising edge at TTL/CMOSIN by −700 ps at +27°C. Jitter transfer bandwidth is 200 kHz with <0.08 dB peaking.

Key Specifications

Parameter	Value and Actual Design Meaning
Synthesis Frequency	155.52 MHz output locked to 19.44 MHz (×8) or 9.72 MHz (×16) input - enables direct bit-clock generation for OC-3/STM-1 systems.
Output Jitter	2.0° RMS typical - meets SONET GR-1244-CORE jitter compliance for transmit clocking.
Supply Voltage	+5 V single supply (4.5 V to 5.5 V) - eliminates need for dual-rail supplies in telecom line cards.
Power Dissipation	90 mW at +5 V - supports thermal design in dense backplane timing modules without forced air.
Input Compatibility	TTL/CMOS (Pin 10) or differential PECL (Pins 12/13) - allows flexible reference sourcing from FPGA clocks or recovered data streams.
Operating Temperature	−40°C to +85°C - qualified for industrial and outdoor telecom equipment deployment.
Output Interface	10 kΩ ECL/PECL-compatible differential pair (Pins 4/5) - directly drives 50 Ω transmission lines with AC-coupled termination.

Pinout & Package

AD809BRZ-REEL is housed in a 16-pin narrow-body SOIC (R-16A) package, 150 mil width, with θ_JA = 110°C/W. Pin 1 identifier is marked by a beveled corner; pins are numbered counterclockwise.

Pin/Terminal	Circuit Role	Design Meaning
1, 2	PECLINN / PECLIN	Differential PECL reference input pair - accepts 155.52 MHz recovered clock; unused when TTL/CMOSIN selected.
4, 5	CLKOUTN / CLKOUT	Differential 155.52 MHz PECL output - provides low-skew, matched delay complementary clock for serializer ICs.
10	TTL/CMOSIN	Single-ended reference input - used with 19.44/9.72 MHz system clock; Pins 12/13 tied to AVEE to enable mux selection.
12, 13	CLKINN / CLKIN	Differential PECL reference input - active when MUX = logic high; requires 50 Ω termination to VCC2.
15	MUX	Reference source select control - TTL-level input that routes either TTL/CMOSIN (low) or CLKIN/CLKINN (high) to PFD.
7, 8	CF1 / CF2	Loop damping capacitor connections - sets PLL ζ factor; 22 nF yields ζ = 10 for optimal jitter suppression.
3, 6, 11, 14	VCC2 / VCC1 / AVCC1 / AVCC2	Separate digital/analog power rails - isolates noise-sensitive PLL core (AVCC1/AVCC2) from output driver (VCC2).
9, 16	AVEE / VEE	Analog/digital ground references - AVEE serves as analog return for internal bias; VEE is digital return for PECL outputs.

Key Features

Feature	Design Value
Auto-selecting reference mux	Hardware-controlled switch between TTL/CMOS and differential PECL inputs - enables loop-timed or master-timed architectures without external logic.
On-chip VCO with no external tuning	Integrated LC-VCO eliminates varactor diodes, trim caps, or inductors - reduces BOM count and layout sensitivity in high-speed clock trees.
Low-jitter PLL architecture	2.0° RMS output jitter with 200 kHz jitter transfer bandwidth - suppresses upstream reference jitter while maintaining tight phase noise floor.
Single-supply +5 V operation	Eliminates negative rail requirement - simplifies power delivery in +5 V-only systems such as access node line cards and media converters.
Phase skew control	Falling edge of CLKOUTN leads TTL/CMOSIN rising edge by −700 ps at +27°C - enables precise setup/hold alignment for parallel data interfaces.

Applications

SONET OC-3 Line Card	Fiber-in-the-Loop Terminal
Use Scenario: Generating transmit bit clock for 155.52 Mbps serial data path in optical line interface module. IC Role / Device Role / Timing Role: Primary frequency synthesizer providing low-jitter 155.52 MHz clock to serializer IC and framer. Use Value: Meets GR-253-CORE jitter mask for OC-3 transmit clock; eliminates external crystal oscillator and discrete PLL components.	Use Scenario: Recovering and regenerating bit clock from incoming 155.52 Mbps fiber signal in remote terminal unit. IC Role / Device Role / Timing Role: Loop-timed clock synthesizer using recovered data as reference input via PECLIN/PECLINN pins. Use Value: Supports hitless clock switching between local and recovered references; maintains synchronization during signal loss per ITU-T G.823.
SDH STM-1 Add-Drop Multiplexer	Optical Network Test Equipment
Use Scenario: Providing synchronized 155.52 MHz clock across multiple tributary processing paths in metro ADM chassis. IC Role / Device Role / Timing Role: Distributed timing node receiving 19.44 MHz backplane reference and generating local 155.52 MHz outputs. Use Value: Enables deterministic phase alignment across slots via common reference distribution; supports multi-slot clock fanout with <2 ps skew.	Use Scenario: Stimulating jitter tolerance testing of receiver ICs using programmable low-jitter clock source. IC Role / Device Role / Timing Role: Precision clock generator with adjustable loop damping (via CF1/CF2) to emulate various jitter transfer profiles. Use Value: Allows validation of device jitter transfer function per IEEE 802.3 Clause 40; 22 nF CF yields ζ = 10 for flat response.

SONET OC-3 Line Card

Fiber-in-the-Loop Terminal

Use Scenario: Generating transmit bit clock for 155.52 Mbps serial data path in optical line interface module.

IC Role / Device Role / Timing Role: Primary frequency synthesizer providing low-jitter 155.52 MHz clock to serializer IC and framer.

Use Value: Meets GR-253-CORE jitter mask for OC-3 transmit clock; eliminates external crystal oscillator and discrete PLL components.

Use Scenario: Recovering and regenerating bit clock from incoming 155.52 Mbps fiber signal in remote terminal unit.

IC Role / Device Role / Timing Role: Loop-timed clock synthesizer using recovered data as reference input via PECLIN/PECLINN pins.

Use Value: Supports hitless clock switching between local and recovered references; maintains synchronization during signal loss per ITU-T G.823.

SDH STM-1 Add-Drop Multiplexer

Optical Network Test Equipment

Use Scenario: Providing synchronized 155.52 MHz clock across multiple tributary processing paths in metro ADM chassis.

IC Role / Device Role / Timing Role: Distributed timing node receiving 19.44 MHz backplane reference and generating local 155.52 MHz outputs.

Use Value: Enables deterministic phase alignment across slots via common reference distribution; supports multi-slot clock fanout with <2 ps skew.

Use Scenario: Stimulating jitter tolerance testing of receiver ICs using programmable low-jitter clock source.

IC Role / Device Role / Timing Role: Precision clock generator with adjustable loop damping (via CF1/CF2) to emulate various jitter transfer profiles.

Use Value: Allows validation of device jitter transfer function per IEEE 802.3 Clause 40; 22 nF CF yields ζ = 10 for flat response.

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
LMX2531LQ1725E	Integrated fractional-N PLL with 1725 MHz max VCO; requires external loop filter; 1.1° RMS jitter at 155.52 MHz.	Supports frequency agility and spread-spectrum clocking; lacks auto-mux and fixed ×8/×16 modes.	Choose when programmable output frequency or fine resolution is required; not drop-in for AD809BRZ-REEL's fixed-ratio use case.
ICS8430M-01LFT	LVDS output; 155.52 MHz fixed-frequency clock generator (no PLL); 0.8 ps RMS jitter; no input mux or VCO.	Used only as crystal-less clock buffer; cannot synthesize from lower-frequency reference.	Choose only if reference is already at 155.52 MHz and jitter budget is tighter; incompatible with 19.44/9.72 MHz input requirement.

Compared with LMX2531LQ1725E and ICS8430M-01LFT, the AD809BRZ-REEL uniquely combines fixed-ratio synthesis, hardware input mux, and integrated VCO in a single +5 V SOIC package-making it optimal for cost-sensitive, high-volume SONET/SDH bit-clock generation where frequency agility is unnecessary.

Availability

AD809BRZ-REEL is available at Aetrix Electronics and suitable for SONET OC-3 line cards, SDH STM-1 add-drop multiplexers, and Fiber-in-the-Loop terminals requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for AD809BRZ-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The AD809BRZ-REEL belongs to Analog Devices' precision timing and clock generation product line, designed specifically for telecom infrastructure applications demanding low-jitter, fixed-ratio frequency synthesis in harsh environmental conditions.

FAQ

What reference frequencies does the AD809BRZ-REEL accept?

The AD809BRZ-REEL accepts two precise reference frequencies: 19.44 MHz for ×8 synthesis or 9.72 MHz for ×16 synthesis. These correspond to SONET OC-3 and SDH STM-1 base rates. The device uses an internal multiplexer to select between TTL/CMOS (Pin 10) or differential PECL (Pins 12/13) inputs based on the logic level applied to Pin 15 (MUX). Both input types are supported simultaneously in the same design.

Does the AD809BRZ-REEL require external passive components to operate?

The AD809BRZ-REEL requires two external ceramic capacitors (CF1 and CF2) for loop damping-typically 22 nF each to achieve ζ = 10-and standard power supply decoupling (0.1 µF near each VCC/AVCC pin and 10 µF bulk cap on VCC2). No external inductors, varactors, or crystal resonators are needed, as the VCO and reference mux are fully integrated. Termination resistors (49.9 Ω) are required only for PECL inputs/outputs.

How does the AD809BRZ-REEL handle loss of input signal?

The AD809BRZ-REEL is designed to drift low in frequency-by approximately 20%-when no valid input signal is present at either reference input. This fail-safe behavior prevents uncontrolled high-frequency oscillation and ensures downstream logic remains in a known state. The device continues drawing ~22 mA but ceases locked output; recovery occurs automatically within milliseconds once reference is restored.

What is the phase relationship between AD809BRZ-REEL inputs and outputs?

The AD809BRZ-REEL output is phase-aligned such that the falling edge of CLKOUTN (Pin 4) occurs 700 ps before the rising edge of TTL/CMOSIN (Pin 10) at +27°C. This skew remains stable across temperature (−35°C to +100°C), varying from −1000 ps to −250 ps. For PECL reference inputs, phase tracking is maintained relative to the differential zero-crossing point, preserving deterministic timing margins in serializer interfaces.

Can the AD809BRZ-REEL operate from a −5.2 V supply?

No-the AD809BRZ-REEL is specified only for +5 V single-supply operation (4.5 V to 5.5 V). While early AD809 documentation mentions "+5 V or –5.2 V" in legacy revisions, the AD809BRZ-REEL variant-as confirmed by Analog Devices' current datasheet revision A and ordering guide-is rated exclusively for positive 5 V supply. Using negative voltage risks permanent damage and violates absolute maximum ratings.

AD809BRZ-REEL Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock/Frequency Synthesizer

PLL:: Yes

Input:: CMOS, ECL, PECL, TTL

Output:: ECL, PECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:1

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 155.52MHz

Divider/Multiplier:: No/No

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-SOIC

AD809BRZ-REEL FAQ

1.How can I place an order for AD809BRZ-REEL through Aetrix?

Please submit a Request for Quotation (RFQ) for AD809BRZ-REEL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD809BRZ-REEL reliable?

The price and inventory of AD809BRZ-REEL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD809BRZ-REEL is usually 5 days.

3.What payment methods are accepted for AD809BRZ-REEL?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD809BRZ-REEL transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD809BRZ-REEL?

AD809BRZ-REEL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD809BRZ-REEL order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD809BRZ-REEL?

For technical support, including AD809BRZ-REEL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD809BRZ-REEL requirements.

6.How does Aetrix verify that AD809BRZ-REEL is sourced from the original manufacturer or authorized distributors?

All AD809BRZ-REEL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD809BRZ-REEL meets industry standards.

7.What is the process for return or replacement of AD809BRZ-REEL?

All AD809BRZ-REEL units undergo pre-shipment inspection (PSI). If there is an issue with AD809BRZ-REEL, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD809BRZ-REEL part is unused and in its original packaging.

Return procedure for AD809BRZ-REEL:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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