Analog Devices Inc. AD8159ASVZ

Overview

AD8159ASVZ from Analog Devices is a quad-lane, protocol-agnostic 2:1 multiplexer / 1:2 demultiplexer IC designed for high-speed serial backplane routing. It supports up to 3.2 Gbps per lane (NRZ), provides two levels of input equalization and four levels of output pre-emphasis, and operates across −40°C to +85°C in a 100-lead TQFP_EP package. It enables redundancy switching in XAUI, PCIe, and Fibre Channel systems.

For engineers reviewing the AD8159ASVZ datasheet, AD8159ASVZ pinout, AD8159ASVZ application, or AD8159ASVZ equivalent, key selection criteria include deterministic jitter (20 ps p-p), lane-to-lane skew (100 ps), unicast/bicast configuration, port-level loopback, and reversible Port C I/O for ASIC pinout alignment.

Technical Context

The AD8159ASVZ implements independent lane switching via SEL[3:0], with each lane supporting dc–3.2 Gbps NRZ signaling. Its architecture integrates receive equalization (EQ) per port (0 dB or 6 dB gain) and transmit pre-emphasis (PE) per port (0–4.9 dB), enabling compensation over up to 40 inches of FR4 backplane including connectors.

It features three differential ports: Port A and Port B are dedicated 4-lane inputs (mux side) or outputs (demux side); Port C is bidirectional and reversible via REVERSE_C, supporting both 2:1 mux and 1:2 demux functions simultaneously under control logic including BICAST, LB_A/B/C, and EQ/PE configuration pins.

Key Specifications

Pinout & Package

AD8159ASVZ is housed in a 100-lead TQFP_EP (exposed paddle) package, 14 mm × 14 mm, 0.5 mm pitch. The exposed paddle must be soldered to VEE for thermal compliance (θJC = 13°C/W). Pin count includes 12 differential CML-compatible inputs, 12 differential outputs, 4 lane-select controls (SEL[3:0]), 6 pre-emphasis controls (PE_A/B/C[1:0]), 3 loopback enables (LB_A/B/C), BICAST, REVERSE_C, EQ_A/B/C, and multiple termination supply rails (VTTI, VTTO, VTTIO, VTTOI).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed serial mux/demux applications.

Compared with SN65LVCP22 and MAX9158, AD8159ASVZ uniquely combines quad-lane independence, bicast capability, Port C reversibility, on-chip EQ/PE, and integrated termination - making it the only option qualified for full-featured XAUI/PCIe redundancy switching in industrial temperature range.

Availability

AD8159ASVZ is available at Aetrix Electronics and suitable for XAUI backplane redundancy, PCIe Gen1 link testing, and Fibre Channel failover systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for AD8159ASVZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The AD8159ASVZ belongs to Analog Devices' high-speed interface portfolio, engineered specifically for protocol-transparent serial link redundancy, signal integrity enhancement, and backplane channel compensation in telecom and data center infrastructure.

FAQ

What is the maximum supported data rate per lane for AD8159ASVZ?

The AD8159ASVZ supports up to 3.2 Gbps per lane using NRZ signaling. This rate is validated across the full operating temperature range (−40°C to +85°C) with deterministic jitter ≤20 ps p-p and BER <10⁻¹⁶. It fully complies with XAUI (3.125 Gbps), PCIe Gen1 (2.5 Gbps), and Fibre Channel 2.125 Gbps standards.

Does AD8159ASVZ require external termination resistors?

No, AD8159ASVZ includes on-chip 100 Ω differential termination with ±10% tolerance and 0.15 Ω/°C temperature coefficient. External termination is optional and only needed when custom impedance matching or AC coupling is used. The internal termination simplifies layout and improves signal integrity at 3.2 Gbps.

How does the REVERSE_C pin affect AD8159ASVZ functionality?

The REVERSE_C pin (Pin 12) toggles the I/O direction of all Port C pins: when low, Pins 77–87 act as inputs and 89–99 as outputs; when high, their roles swap. This allows direct connection to ASICs with mirrored pinouts without redesigning the PCB, preserving signal integrity and reducing development time for AD8159ASVZ-based systems.

Can AD8159ASVZ operate with 2.5 V I/O supplies?

Yes, AD8159ASVZ supports flexible I/O supply voltages down to 2.5 V on VTTO, VTTI, VTTOI, and VTTIO rails while maintaining full 3.2 Gbps operation and specified jitter performance. Core supply remains fixed at 3.3 V (VCC), but I/O voltage scaling enables interoperability with 2.5 V CML or LVDS receivers/transmitters in mixed-voltage systems.

What is the thermal design requirement for AD8159ASVZ?

AD8159ASVZ uses an exposed paddle (ePAD) that must be soldered to the VEE ground plane to achieve θJC = 13°C/W. Without ePAD connection, junction-to-case thermal resistance degrades significantly. For 1 W typical power dissipation, this ensures junction temperature stays within spec under still-air conditions across the full −40°C to +85°C ambient range.