Analog Devices Inc. AD8332ACP-R2
- Part No.:
- AD8332ACP-R2
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Amplifiers
- Package:
- 32-WFQFN Exposed Pad, CSP
- Datasheet:
-
AD8332ACP-R2.pdf
- Description:
- IC VGA DUAL W/PREAMP LN 32-LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD8332ACP-R2 from Analog Devices is a dual-channel, ultralow-noise, linear-in-dB variable gain amplifier (VGA) with integrated preamplifier and programmable input impedance. It delivers 19 dB LNA gain, 48 dB VGA gain range (−4.5 dB to +43.5 dB in LO mode), 100 MHz −3 dB bandwidth, and 40 nV/√Hz output-referred noise at LO gain-optimized for ultrasound time-gain control and high-speed differential ADC driving.
For engineers reviewing the AD8332ACP-R2 datasheet, AD8332ACP-R2 pinout, AD8332ACP-R2 application, or AD8332ACP-R2 equivalent, key selection criteria include its dual-channel architecture, LFCSP-32 package with exposed thermal pad, 5 V single-supply operation, selectable 3.5 dB / 15.5 dB postamp gain, and active input impedance matching via external RIZ.
Technical Context
The AD8332ACP-R2 integrates two independent signal paths, each comprising an ultralow-noise LNA (0.74 nV/√Hz voltage noise, 2.5 pA/√Hz current noise), a 48 dB X-AMP® VGA with precise 50 dB/V linear-in-dB gain control, and a pin-selectable postamplifier (3.5 dB or 15.5 dB). Its differential architecture ensures −98 dB channel-to-channel crosstalk and low distortion (HD2 = −62 dBc at 10 MHz).
Gain scaling is factory-trimmed for ±0.1 dB channel-to-channel matching across 0.1 V–0.95 V control voltage; overload recovery is 5 ns, and group delay variation is ±2 ns over 5–50 MHz. The device supports active termination matching (RIN programmable from 50 Ω to 6 kΩ) without degrading noise performance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LNA Voltage Noise | 0.74 nV/√Hz - enables detection of weak signals in ultrasound front-ends without amplifying thermal noise floor |
| VGA Bandwidth | 100 MHz (−3 dB) - supports wideband I/Q processing up to 100 MHz without gain peaking or phase distortion |
| Output-Referred Noise | 40 nV/√Hz (LO gain) - matches dynamic range of 12-bit ADCs with ≥70 dB SNR at 10 MSPS |
| Gain Range | −4.5 dB to +43.5 dB (LO mode); 7.5 dB to 55.5 dB (HI mode) - provides 48 dB linear-in-dB control for AGC loop stability |
| Channel Crosstalk | −98 dB - prevents signal leakage between channels in dual-beam ultrasound or I/Q demodulation |
| Overload Recovery | 5 ns - maintains signal integrity during rapid echo amplitude transitions in sonar pulse-echo systems |
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5 V industrial and medical power rails; no external regulators needed |
Pinout & Package
The AD8332ACP-R2 is housed in a 32-lead LFCSP (Lead Frame Chip Scale Package) with 5 mm × 5 mm footprint and exposed thermal pad requiring PCB ground connection for thermal dissipation, noise reduction, and mechanical reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LON1, LOP1, LON2, LOP2 | LNA inverting/noninverting outputs (per channel) | Differential LNA outputs drive VGA inputs; require matched 50 Ω routing to preserve CMRR > 60 dB |
| VIN1, VIP1, VIN2, VIP2 | VGA inverting/noninverting inputs | Accept differential input from LNA; high-impedance node (10 MΩ) minimizes loading on preceding stage |
| VOH1, VOL1, VOH2, VOL2 | VGA noninverting/inverting outputs | True differential outputs drive ADC inputs directly; support 4.5 V p-p swing into 500 Ω load |
| GAIN | Analog gain control voltage input | 0–1.0 V input sets gain with 50 dB/V slope; 0.1 V–0.95 V range yields ±0.2 dB gain law conformance |
| HILO | Gain range select logic input | Logic-high selects HI gain mode (7.5–55.5 dB); logic-low selects LO mode (−4.5–+43.5 dB) |
| RCLMP | Output clamping level resistor terminal | External resistor sets clamping threshold (e.g., 2.74 kΩ → ±50 mV clamp error at 1 V p-p output) |
| ENBL, ENBV | Independent LNA and VGA enable inputs | Enable/disable LNA (ENBL) or VGA (ENBV) separately for power gating in multi-stage AGC designs |
| VCM1, VCM2 | Per-channel common-mode voltage reference | Sets output common-mode level (1.5–3.5 V range); decouples ADC reference from VGA biasing |
| VPS1, VPS2, VPSV | Separate LNA and VGA supply pins | Isolates LNA and VGA power domains to prevent supply coupling; all accept 4.5–5.5 V |
| Exposed Pad | Thermal and electrical ground | Must be soldered to solid PCB ground plane with ≥9 thermal vias to achieve θJA = 33°C/W |
Key Features
| Feature | Design Value |
|---|---|
| Ultralow-noise LNA with programmable RIN | Adjusts input impedance from 50 Ω to 6 kΩ using single external resistor-maintains 0.74 nV/√Hz noise while matching transducer or filter source impedance |
| Dual independent VGA channels | Each channel has dedicated GAIN, HILO, RCLMP, VCM, and enable pins-enables asymmetric gain control for beamforming or I/Q path calibration |
| Selectable postamp gain | 3.5 dB or 15.5 dB pin-selectable gain optimizes noise-vs.-headroom trade-off for 10-bit vs. 12-bit ADC interfaces |
| Active output clamping | User-defined clamping level prevents ADC saturation during transient overload; <50 mV accuracy at 1 V p-p output |
| Factory-trimmed gain matching | ±0.1 dB channel-to-channel gain matching across full control voltage range-reduces calibration overhead in dual-path systems |
Applications
| Ultrasound Time-Gain Control (TGC) | I/Q Signal Processing |
|---|---|
|
Use Scenario: Amplifies weak returning echoes in phased-array ultrasound probes, compensating for depth-dependent attenuation. IC Role / Device Role / Timing Role: Dual-channel VGA performs real-time, depth-synchronized gain adjustment per scan line; LNA captures microvolt-level echoes before digitization. Use Value: 0.74 nV/√Hz LNA noise and 40 nV/√Hz VGA noise preserve SNR for sub-100 µm tissue resolution; 5 ns overload recovery handles near-field clutter rejection. |
Use Scenario: Splits and independently gains in-phase (I) and quadrature (Q) baseband signals in RF receivers and software-defined radios. IC Role / Device Role / Timing Role: Two matched VGA channels process I and Q paths with identical gain law and timing response-critical for image rejection ratio (IRR) > 45 dB. Use Value: −98 dB crosstalk and ±0.1 dB gain matching ensure I/Q imbalance < 0.1° phase error; 100 MHz bandwidth supports >20 MHz complex IF bandwidths. |
| High-Speed Dual ADC Driver | AGC System Front-End |
|
Use Scenario: Drives differential inputs of 10-bit/12-bit, 40–100 MSPS ADCs in test equipment and radar digitizers. IC Role / Device Role / Timing Role: VGA + postamp delivers 4.5 V p-p differential output swing with 40 nV/√Hz noise-directly interfaces to ADCs without external op-amps. Use Value: Output-referred noise of 40 nV/√Hz enables ≥72 dB SNR with 12-bit ADCs; selectable 3.5 dB/15.5 dB postamp gain matches ADC full-scale range. |
Use Scenario: Serves as core gain element in closed-loop automatic gain control circuits for optical receivers, sonar preamps, and instrumentation front-ends. IC Role / Device Role / Timing Role: Linear-in-dB gain control (50 dB/V) simplifies AGC loop design; fast 500 ns response to 48 dB gain steps ensures stable loop dynamics. Use Value: Absolute gain error ≤ ±0.3 dB over 0.1–0.95 V control range reduces need for digital correction; 100 MHz bandwidth supports AGC loops up to 10 MHz update rate. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar variable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD8331ARQZ | Single-channel, 20-lead QSOP, 120 MHz bandwidth, 125 mW/channel power | Lower channel count; lacks dual-channel synchronization; higher bandwidth but higher noise (48 nV/√Hz) | Choose when space-constrained single-channel TGC or AGC is required and 120 MHz bandwidth is critical |
| AD8334ACPZ-REEL7 | Quad-channel, 64-lead LFCSP, 100 MHz bandwidth, 29.5 mA/channel quiescent current | Higher integration density; same noise and bandwidth specs; requires more complex layout and thermal management | Choose for multi-beam ultrasound or parallel I/Q processing where four matched channels justify added complexity |
Compared with AD8331ARQZ and AD8334ACPZ-REEL7, the AD8332ACP-R2 uniquely balances dual-channel integration, 100 MHz bandwidth, 40 nV/√Hz noise, and LFCSP-32 thermal performance-making it optimal for compact, high-fidelity dual-path medical and communications signal chains.
Availability
AD8332ACP-R2 is available at Aetrix Electronics and suitable for ultrasound imaging systems, I/Q demodulators, high-speed data acquisition, and automatic gain control circuits requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for AD8332ACP-R2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, serving precision instrumentation, healthcare, communications, and industrial markets.
The AD833x family was designed specifically for ultralow-noise, wideband variable gain applications in medical ultrasound, sonar, and high-speed data conversion-emphasizing noise performance, gain accuracy, and channel matching over general-purpose amplification.
FAQ
What is the operating temperature range for the AD8332ACP-R2?
The AD8332ACP-R2 is specified for operation from −40°C to +85°C ambient temperature. This industrial-grade range supports deployment in portable ultrasound devices, outdoor sonar systems, and factory-floor test equipment without derating. Thermal performance relies on proper soldering of the exposed pad to a grounded PCB plane with ≥9 thermal vias to maintain θJA = 33°C/W.
How does the AD8332ACP-R2 achieve programmable input impedance without degrading noise performance?
The AD8332ACP-R2 uses an active impedance-matching circuit that adjusts LNA input resistance (RIN) from 50 Ω to 6 kΩ via a single external resistor (RIZ) connected to the LMD pin. Unlike passive networks, this technique preserves the 0.74 nV/√Hz voltage noise and 2.5 pA/√Hz current noise because the matching is implemented within the LNA's feedback structure-not as a lossy external divider.
Can the AD8332ACP-R2 drive a 12-bit ADC directly, and what postamp gain setting is recommended?
Yes, the AD8332ACP-R2 can drive a 12-bit ADC directly. For optimal SNR, use the 3.5 dB postamp gain setting (HILO = LO) to minimize output-referred noise (40 nV/√Hz) while delivering sufficient swing (±1.125 V around VCM). This configuration matches typical 12-bit ADC full-scale ranges (2.0–2.5 V p-p) without clipping or excessive headroom loss.
What is the purpose of separate ENBL and ENBV pins on the AD8332ACP-R2?
The ENBL (LNA Enable) and ENBV (VGA Enable) pins allow independent power gating of the LNA and VGA stages. This enables flexible power management-for example, disabling only the VGA during standby while keeping the LNA active for wake-up detection, or powering down both stages to achieve <600 µA total shutdown current. Each pin accepts 0–1.0 V logic-low to disable.
Does the AD8332ACP-R2 support differential input to differential output operation throughout its signal chain?
Yes, the AD8332ACP-R2 supports true differential operation end-to-end: the LNA accepts single-ended input (INH) but produces differential outputs (LON/LOP); the VGA accepts differential input (VIN/VIP) and delivers differential output (VOH/VOL). This architecture achieves −98 dB crosstalk and superior second/third-order distortion performance (HD2 = −62 dBc at 10 MHz), essential for high-fidelity I/Q and ultrasound applications.
AD8332ACP-R2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad, CSP
- Packaging:
- Cut Tape (CT)
- Product Status:
- Obsolete
- Type:
- Variable Gain Amplifier
- Applications:
- Signal Processing
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-LFCSP-WQ (5x5)
AD8332ACP-R2 FAQ
1.How can I place an order for AD8332ACP-R2 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD8332ACP-R2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD8332ACP-R2 reliable?
The price and inventory of AD8332ACP-R2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD8332ACP-R2 is usually 5 days.
3.What payment methods are accepted for AD8332ACP-R2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD8332ACP-R2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD8332ACP-R2?
AD8332ACP-R2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD8332ACP-R2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD8332ACP-R2?
For technical support, including AD8332ACP-R2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD8332ACP-R2 requirements.
6.How does Aetrix verify that AD8332ACP-R2 is sourced from the original manufacturer or authorized distributors?
All AD8332ACP-R2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD8332ACP-R2 meets industry standards.
7.What is the process for return or replacement of AD8332ACP-R2?
All AD8332ACP-R2 units undergo pre-shipment inspection (PSI). If there is an issue with AD8332ACP-R2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD8332ACP-R2 part is unused and in its original packaging.
Return procedure for AD8332ACP-R2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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