Analog Devices Inc. AD8345AREZ

Overview

AD8345AREZ from Analog Devices is a silicon RFIC quadrature modulator operating from 140 MHz to 1000 MHz, delivering +2.5 dBm P1dB output power at 800 MHz with −155 dBm/Hz noise floor, 0.5° RMS phase error, and 0.2 dB amplitude balance. It serves as the IF transmit modulator in GSM, PCS, W-CDMA, and digital TV systems, enabling direct QPSK/QAM modulation with single-ended 50 Ω RF output at VOUT.

For engineers reviewing the AD8345AREZ datasheet, AD8345AREZ pinout, AD8345AREZ application, or AD8345AREZ equivalent, this page delivers verified RF performance data, validated baseband interface requirements, confirmed TSSOP_EP package mapping, and real-world sideband suppression and LO leakage behavior across temperature and frequency.

Technical Context

The AD8345AREZ integrates a polyphase phase splitter to generate precise I/Q LO signals, differential voltage-to-current converters for baseband inputs (IBBP/IBBN/QBBP/QBBN), and double-balanced Gilbert-cell mixers - all biased via a PTAT bandgap reference controlled by ENBL. Its architecture supports ac-coupled differential LO drive and requires external dc biasing of baseband inputs to 0.7 V.

LO input matching relies on internal 1.8 V dc bias on LOIP/LOIN, with S11 optimized using balun coupling or 50 Ω termination; RF output at VOUT is dc-coupled and internally matched to 50 Ω, exhibiting −20 dB return loss. Performance is specified over −40°C to +85°C with supply range 2.7 V to 5.5 V and active current draw of 50–78 mA.

Key Specifications

Pinout & Package

AD8345AREZ is housed in a 16-lead TSSOP_EP package with exposed paddle for thermal dissipation (θJA = 30°C/W when soldered down). Ground pins are segregated by functional block (COM1 for LO, COM2 for output stage, COM3 for baseband/V-to-I/mixer core) to minimize coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quadrature modulator applications.

Compared with AD8345AREZ, AD8346AREZ trades 1 dB output and 7 dB noise floor for lower power, while AD8349AREZ extends frequency coverage to 3 GHz at the cost of supply flexibility - neither offers drop-in replacement without verifying system-level linearity and noise requirements.

Availability

AD8345AREZ is available at Aetrix Electronics and suitable for cellular infrastructure, fixed wireless access, digital TV broadcast, and test instrumentation requiring stable component supply across extended temperature ranges and multi-year production cycles.

Supply support for AD8345AREZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and RF ICs, founded in 1965 and headquartered in Wilmington, MA. The company specializes in precision signal processing for communications, industrial, and aerospace applications.

The AD8345AREZ belongs to Analog Devices' RF Modulator product line, designed specifically for direct-conversion transmitters in wireless infrastructure and broadband systems - emphasizing phase accuracy, wideband linearity, and integration to replace discrete modulator assemblies.

FAQ

What is the minimum LO drive level required for stable operation of the AD8345AREZ?

The AD8345AREZ specifies a minimum LO drive level of −10 dBm and a typical value of −2 dBm for optimal noise performance. At −2 dBm, the device achieves its lowest noise floor of −155 dBm/Hz; reducing LO power to −10 dBm increases noise by ~0.3 dB. Operation below −10 dBm risks degraded sideband suppression and increased LO leakage, as confirmed in Figure 21 and Table 1 of the AD8345AREZ datasheet Rev. B.

Can the AD8345AREZ operate with a 2.7 V supply while maintaining full RF output power?

No - at 2.7 V supply, the AD8345AREZ output power drops significantly: typical SSB output is −6 dBm at 800 MHz versus +2.5 dBm at 5 V. The datasheet specifies 200 mV_p-p differential baseband drive (vs. 1.2 V_p-p at 5 V) to avoid clipping, resulting in ~18 dB lower output. Full-power operation requires ≥4.5 V supply per Figure 3 and Table 1.

How is LO leakage compensated in the AD8345AREZ, and does it require hardware modification?

LO leakage in the AD8345AREZ is compensated by applying adjustable dc offset voltages to the I and Q baseband inputs (IBBP/IBBN/QBBP/QBBN), not by altering the 0.7 V common-mode bias. This is implemented via programmable DAC offsets in the signal chain - no PCB changes are needed. The procedure is detailed in the "Reduction of LO Leakage" section (Page 13) and validated to hold across −40°C to +85°C.

Is the AD8345AREZ pin-compatible with the AD8346AREZ and AD8349AREZ, and can they share the same PCB layout?

Yes - the AD8345AREZ, AD8346AREZ, and AD8349AREZ share identical 16-lead TSSOP_EP package dimensions, pin numbering, and pin functions per Figures 2 and 28 of the datasheet. All three devices use the same decoupling scheme (1000 pF + 0.01 μF on VPS1/VPS2) and grounding structure (segregated COM1/COM2/COM3), enabling layout reuse across the family.

What baseband input configuration is required to achieve 1.3% EVM on the AD8345AREZ?

To achieve 1.3% EVM, the AD8345AREZ requires differential baseband drive at 1.2 V_p-p with 0.7 V common-mode bias on both I and Q channels, LO drive at −2 dBm, and operation at 25°C with 5 V supply. This configuration is validated in the "RESPONSE TO CDMA IS95" section (Table 1) and correlates directly with the 0.5° RMS phase error and 0.2 dB amplitude balance specifications.