Analog Devices Inc. AD8367ARUZ
- Part No.:
- AD8367ARUZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AD8367ARUZ.pdf
- Description:
- IC VARIABLE GAIN 1 CIRC 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:252
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Product details
Overview
AD8367ARUZ from Analog Devices is a 500 MHz linear-in-dB variable gain amplifier (VGA) with integrated square-law RMS detector, designed for IF/RF signal conditioning in 200 Ω systems. It delivers −2.5 dB to +42.5 dB analog gain control at 20 mV/dB scaling, supports AGC loop operation with 354 mVrms setpoint, and operates from 2.7 V to 5.5 V supply. It is used in cellular base station IF chains for dynamic signal level management.
For engineers reviewing the AD8367ARUZ datasheet, AD8367ARUZ pinout, AD8367ARUZ application, or AD8367ARUZ equivalent, key selection considerations include its 500 MHz 3 dB bandwidth, 45 dB gain range with ±0.2 dB conformance (100–900 mV VGAIN), 70 MHz noise figure of 6.2 dB at max gain, output IP3 of +36.5 dBm (re 200 Ω), and TSSOP-14 package compatibility with high-speed layout requirements.
Technical Context
The AD8367ARUZ implements Analog Devices' X-AMP® architecture: a 9-stage 200 Ω resistive ladder attenuator (5 dB/stage) followed by a 42.5 dB fixed-gain feedback amplifier with 100 GHz gain-bandwidth product. Gain is controlled via voltage applied to GAIN pin, with MODE pin selecting positive-slope (+20 mV/dB) or negative-slope (−20 mV/dB) response - the latter required for AGC mode.
Its on-chip square-law detector provides RSSI output at DETO pin referenced to 354 mVrms, enabling closed-loop automatic gain control using external CAGC. Output centering is maintained via DECL/HPFL loop with user-defined corner frequency, while input presents nominal 200 Ω impedance and output includes internal 50 Ω series resistor optimized for 200 Ω load matching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | −2.5 dB to +42.5 dB: full 45 dB span usable across 10 MHz–500 MHz with <±0.2 dB linearity error over 40 dB at 70 MHz. |
| 3 dB Bandwidth | 500 MHz at mid-gain: enables wideband IF amplification up to cellular/WiMAX frequencies without gain peaking. |
| Gain Scaling | 20 mV/dB (±0.1 mV/dB typical): precise linear-in-dB control allows direct dB-domain system calibration without lookup tables. |
| Output IP3 | +36.5 dBm (re 200 Ω) at 70 MHz: high linearity supports multi-carrier signals in broadband access infrastructure. |
| Noise Figure | 6.2 dB at maximum gain, 25°C: low NF preserves SNR in weak-signal receiver front-ends. |
| Supply Range | 2.7 V to 5.5 V single supply: compatible with modern low-voltage RF subsystems and simplifies power rail design. |
| Power Consumption | 26 mA at 5 V, max gain: enables thermally constrained designs in dense baseband modules. |
Pinout & Package
AD8367ARUZ is housed in a 14-lead TSSOP package (4.4 mm × 5.0 mm, 0.65 mm pitch), rated for −40°C to +85°C industrial operation. Pin 1 is ICOM (signal common), and all ground pins (ICOM ×3, OCOM) must connect to low-impedance ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INPT (Pin 3) | Signal Input | 200 Ω resistive ladder input node; requires ac-coupling if dc-biased; max 700 mVp-p to avoid overload. |
| GAIN (Pin 5) | Analog Gain Control | Voltage input (50–950 mV) sets gain per 20 mV/dB law; polarity determined by MODE pin state. |
| MODE (Pin 4) | Gain Slope Selector | HI = positive slope (+20 mV/dB); LO = negative slope (−20 mV/dB), mandatory for AGC operation. |
| DETO (Pin 6) | RMS Detector Output | Current-mode RSSI output; tied to GAIN in AGC mode; 354 mVrms setpoint enables stable output leveling. |
| VOUT (Pin 10) | Signal Output | Buffered output with internal 50 Ω series resistor; requires external ac-coupling; centered at VS/2 when DECL is bypassed. |
| DECL (Pin 9) & HPFL (Pin 13) | Output Centering Loop | Form RC network setting dc centering loop corner frequency; 100 pF yields ~100 kHz corner for stable bias control. |
| ENBL (Pin 2) | Enable Control | Logic HI powers device (26 mA); logic LO reduces current to 1.3–1.8 mA for standby mode. |
Key Features
| Feature | Design Value |
|---|---|
| X-AMP® Architecture | 9-stage 200 Ω ladder + Gaussian interpolator enables monotonic, linear-in-dB gain with <±0.2 dB error over 40 dB range. |
| Integrated Square-Law Detector | On-chip RMS detector with fixed 354 mVrms setpoint eliminates need for external detector IC in AGC loops. |
| AGC Loop Enablement | Single-wire connection (DETO → GAIN) + MODE=LO configures self-contained AGC with <1 μs 6 dB step response (CAGC=100 pF). |
| Input/Output Impedance Optimization | Nominal 200 Ω input and 50 Ω output series resistor preserve distortion performance in standard IF systems without external matching. |
| Wide Supply Range & Low-Power Standby | 2.7–5.5 V operation with 1.3 mA disable current enables use in battery-backed or energy-sensitive infrastructure nodes. |
Applications
| Cellular Base Station IF Chain | Broadband Access Receiver |
|---|---|
Use Scenario: Amplifying and dynamically scaling IF signals (e.g., 70–140 MHz) from downconverters prior to ADC sampling in macrocell BTS. IC Role / Device Role / Timing Role: Linear-in-dB VGA providing programmable gain control and AGC stabilization in analog front-end signal path. Use Value: Maintains constant ADC input level across varying RF signal strength, preventing clipping and preserving ENOB under fading conditions. |
Use Scenario: Signal conditioning in DOCSIS 3.1/4.0 cable modem upstream receivers handling bursty TDMA traffic. IC Role / Device Role / Timing Role: IF gain block with fast AGC response (<1 μs) to track rapid upstream power changes between time slots. Use Value: Enables compliant upstream transmit power control without digital loop latency, reducing upstream packet loss. |
| Power Amplifier Pre-Distortion Loop | High-Speed Data I/O Interface |
Use Scenario: Monitoring PA output via directional coupler and feeding back scaled signal to predistorter DSP in LTE/FDD systems. IC Role / Device Role / Timing Role: High-linearity, wideband VGA acting as amplitude scaler in feedback path of digital pre-distortion (DPD) architecture. Use Value: Delivers +36.5 dBm OIP3 and 500 MHz bandwidth to preserve DPD model accuracy across multi-carrier LTE bands. |
Use Scenario: Level-shifting and gain adjustment of high-speed serial data streams (e.g., JESD204B lanes) between FPGA and RF transceivers. IC Role / Device Role / Timing Role: Voltage-controlled gain stage compensating for trace loss and connector mismatch in high-frequency digital interconnects. Use Value: Provides deterministic 20 mV/dB gain tuning to maintain signal integrity margins without re-routing PCB traces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar variable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADL5330ACPZ-R7 | 50 Ω system design; 2.5–2500 MHz range; 0–30 dB gain; no integrated detector; requires external RSSI circuit. | Used in RF front-ends where wide frequency coverage outweighs need for on-chip AGC. | Select when operating above 500 MHz or requiring 50 Ω impedance match without external transformers. |
| LMH6505MA/NOPB | DC–1.2 GHz bandwidth; 0–30 dB gain; 25 mV/dB scaling; no detector; higher 12.5 mA quiescent current. | Favored in test equipment and wideband oscilloscope channels needing ultra-wideband flatness. | Choose for >500 MHz applications where gain linearity beyond 240 MHz is critical and AGC is implemented digitally. |
Compared with AD8367ARUZ, ADL5330 offers broader RF coverage but lacks integrated AGC capability, while LMH6505 provides superior high-frequency bandwidth at the cost of reduced gain range and no detector - making AD8367ARUZ optimal for 200 Ω IF AGC systems below 500 MHz.
Availability
AD8367ARUZ is available at Aetrix Electronics and suitable for cellular infrastructure, broadband access equipment, and high-speed data interface designs requiring stable component supply, consistent parametric performance, and long-term industrial temperature support.
Supply support for AD8367ARUZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD8367ARUZ belongs to Analog Devices' X-AMP® family of precision variable gain amplifiers, engineered specifically for high-dynamic-range IF signal chains in wireless infrastructure and instrumentation where linear-in-dB control and integrated detection are essential.
FAQ
What is the gain control voltage range for AD8367ARUZ in positive-slope mode?
The AD8367ARUZ accepts a gain control voltage (VGAIN) from 50 mV to 950 mV in positive-slope (MODE = HI) mode, corresponding linearly to −2.5 dB to +42.5 dB gain at 20 mV/dB scaling. Operation outside this range degrades linearity; the device remains functional but gain conformance exceeds ±0.2 dB specification.
How does the AD8367ARUZ implement automatic gain control (AGC)?
The AD8367ARUZ implements AGC using its on-chip square-law detector: when MODE is pulled LOW and DETO is connected to GAIN, the detector compares VOUT to a fixed 354 mVrms setpoint and generates corrective current. An external capacitor (CAGC) from DETO to ground integrates this current to produce the AGC bias voltage that stabilizes output level.
What is the recommended output termination for AD8367ARUZ?
The AD8367ARUZ is optimized for a 200 Ω load, despite its internal 50 Ω output series resistor. Connecting a 200 Ω load ensures specified distortion (OIP3), noise figure, and gain flatness. Using 50 Ω directly causes ~6 dB gain loss and degraded OIP3; reactive matching networks are required for non-200 Ω interfaces.
Can AD8367ARUZ operate from a 3.3 V supply?
Yes, AD8367ARUZ fully supports 3.3 V single-supply operation within its 2.7 V–5.5 V range. At 3.3 V, typical supply current is 24 mA, output swing reduces to ~2.8 Vp-p (RL = 200 Ω), and OIP3 drops to +32.5 dBm - all within datasheet specifications and validated for industrial temperature range.
What is the function of the DECL and HPFL pins on AD8367ARUZ?
DECL and HPFL form a feedback loop that centers the AD8367ARUZ output dc bias at VS/2. A capacitor from HPFL to ground (with optional 100 Ω series resistor) sets the loop's corner frequency; typical 10 nF yields ~10 kHz corner. This prevents output saturation during large ac swings and maintains headroom for full-scale signal handling.
AD8367ARUZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- X-AMP®
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Variable Gain
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- -
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 500 MHz
- Current - Input Bias:
- 27 µA
- Voltage - Input Offset:
- -
- Current - Supply:
- 26mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
AD8367ARUZ FAQ
1.How can I place an order for AD8367ARUZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD8367ARUZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD8367ARUZ reliable?
The price and inventory of AD8367ARUZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD8367ARUZ is usually 5 days.
3.What payment methods are accepted for AD8367ARUZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD8367ARUZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD8367ARUZ?
AD8367ARUZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD8367ARUZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD8367ARUZ?
For technical support, including AD8367ARUZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD8367ARUZ requirements.
6.How does Aetrix verify that AD8367ARUZ is sourced from the original manufacturer or authorized distributors?
All AD8367ARUZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD8367ARUZ meets industry standards.
7.What is the process for return or replacement of AD8367ARUZ?
All AD8367ARUZ units undergo pre-shipment inspection (PSI). If there is an issue with AD8367ARUZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD8367ARUZ part is unused and in its original packaging.
Return procedure for AD8367ARUZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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