Analog Devices Inc. AD9059BRS

Overview

AD9059BRS from Analog Devices is a dual 8-bit, 60 MSPS analog-to-digital converter with on-chip 2.5 V reference, 120 MHz analog bandwidth, and single 5 V supply operation. It delivers 44.5 dB SINAD at 10.3 MHz input and supports simultaneous sampling of two independent analog channels (AINA/AINB) for I/Q demodulation and RGB video digitization.

For engineers reviewing the AD9059BRS datasheet, AD9059BRS pinout, AD9059BRS application, or AD9059BRS equivalent, this page provides verified technical context, real-world timing behavior (t_A = 2.7 ns, t_V = 4.0–6.6 ns), power-down mode (<12 mW), offset binary coding, and SSOP-28 package compatibility - all critical for high-speed data acquisition system design.

Technical Context

The AD9059BRS integrates two independent flash-based ADC cores sharing a single TTL/CMOS-compatible ENCODE input, enabling synchronized sampling without interleaving. Its MagAmp/Flash architecture introduces three-pipeline-stage latency and guarantees simultaneous conversion on the rising edge of ENCODE.

It features dual track-and-hold circuits with 150 kΩ input resistance and 2 pF capacitance, driven by an internal 2.5 V bandgap reference (±10 ppm/°C TC). Digital outputs are configurable for 3 V or 5 V logic via separate VDD pins, while analog and digital supplies (VD/VDD) are isolated to minimize noise coupling.

Key Specifications

Pinout & Package

AD9059BRS is housed in a 28-lead shrink small outline package (SSOP, RS-28), 10.5 mm × 5.6 mm × 1.75 mm body, JEDEC MO-150AH compliant, with 0.65 mm lead pitch and coplanarity ≤0.10 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, medium-speed ADC applications.

Compared with AD9059BRS, AD9057BRS halves channel count but saves 28% board area, while MAX1186EEE+ trades 33% lower speed and missing reference for lower voltage operation - neither matches AD9059BRS's combination of dual-channel sync, internal 2.5 V reference, and 60 MSPS performance in SSOP-28.

Availability

AD9059BRS is available at Aetrix Electronics and suitable for digital communications infrastructure, RGB video capture systems, and medical imaging equipment requiring stable component supply across industrial temperature range (–40°C to +85°C).

Supply support for AD9059BRS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9059BRS belongs to Analog Devices' high-speed data converter product line, designed specifically for cost-sensitive, space-constrained applications demanding dual-channel synchronization, low power, and integrated reference functionality.

FAQ

What is the absolute maximum analog input voltage for the AD9059BRS?

The AD9059BRS specifies an absolute maximum analog input voltage of –0.5 V to VD + 0.5 V. With VD = 5 V, this allows a safe input range of –0.5 V to +5.5 V. However, the functional input range is limited to 1 V_p-p centered at 2.5 V (i.e., 2.0 V to 3.0 V) for full 8-bit accuracy. Exceeding this range causes clipping and missing codes, as confirmed in the DC accuracy specifications table for AD9059BRS.

Does the AD9059BRS support independent power-down of each ADC channel?

No, the AD9059BRS does not support independent power-down. Pin 3 (PWRDN) is a global control that simultaneously disables both ADC A and ADC B. When PWRDN is logic high, both digital outputs enter high-impedance state and total power drops below 12 mW. The datasheet explicitly states "Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be shut down or turned on independently," confirming this behavior for AD9059BRS.

What is the recommended decoupling for the VREF pin on the AD9059BRS?

The AD9059BRS datasheet recommends bypassing the VREF pin to ground with a 0.1 µF ceramic capacitor placed as close as possible to the pin. This minimizes modulation of the 2.5 V reference due to supply noise and ensures stable gain/offset tracking between channels. Figure 2 and the "Using the AD9059" section confirm this value and placement requirement for AD9059BRS, noting that inadequate decoupling degrades SINAD by up to 3 dB.

Can the AD9059BRS operate with a 50% duty cycle encode clock at 60 MSPS?

Yes, the AD9059BRS is fully specified to operate with a 50% duty cycle encode clock at 60 MSPS. The timing diagram (Figure 1) and "Timing" section state that performance is insensitive to moderate variations, and minimum/maximum pulsewidths (t_EHL = 6.7 ns) allow ±10% deviation without degradation. All dynamic performance specs (SINAD, SNR, harmonics) for AD9059BRS are measured under these exact conditions.

Is the AD9059BRS pin-compatible with any evaluation board?

Yes, the AD9059BRS is mounted on the AD9059/PCB evaluation board, which uses the same 28-lead SSOP (RS-28) footprint. The board schematic (Figure 7) shows U1 labeled "AD9059RS", matching the AD9059BRS package variant. This board provides dc/ac coupling options, on-board latching, and configurable reference routing - all validated for AD9059BRS operation per the "Evaluation Board" section.