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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD9200JRSZ

Name: AD9200JRSZ
Brand: Analog Devices Inc.
SKU: AD9200JRSZ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9200JRSZ

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 28-SSOP (0.209", 5.30mm Width)

Datasheet:: AD9200JRSZ.pdf

Description:: IC ADC 10BIT PIPELINED 28SSOP

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Product details

Overview

AD9200JRSZ from Analog Devices is a monolithic 10-bit, 20 MSPS CMOS analog-to-digital converter with on-chip sample-and-hold amplifier and programmable voltage reference. It operates from 2.7 V to 5.5 V, delivers 54.5 dB SINAD at 3.58 MHz, exhibits ±0.5 LSB DNL, and supports IF undersampling up to 135 MHz - used in high-speed communications receivers and digital video digitization.

For engineers reviewing the AD9200JRSZ datasheet, AD9200JRSZ pinout, AD9200JRSZ application, or AD9200JRSZ equivalent, this page provides verified technical context, real-world design meanings for key specs, validated pin functions, confirmed alternatives, and supply-chain support for volume production and industrial embedded deployment.

Technical Context

The AD9200JRSZ implements a multistage differential pipeline architecture enabling 20 MSPS conversion with guaranteed no-missing-codes across –40°C to +85°C. Its switched-capacitor input achieves 300 MHz full-power bandwidth and 2 ps aperture jitter, supporting both single-ended and differential input configurations via MODE/REFSENSE pin strapping.

It integrates a programmable internal reference (1 V or 2 V), out-of-range (OTR) flag, three-state digital outputs, power-down mode (<4 mW), and optional clamp circuitry (enabled in ARS/KST variants). The 28-lead SSOP package supports compact layout while maintaining pin compatibility with AD876 for legacy migration.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	10-bit - defines quantization step size of ~1 mV for 1 V span; enables 1024 discrete amplitude levels per sample.
Sampling Rate	20 MSPS - supports Nyquist-limited baseband signals up to 10 MHz or IF sampling of 135 MHz carriers.
SINAD	54.5 dB at 3.58 MHz - corresponds to ~9.1 effective bits; sufficient for broadcast-quality video digitization.
DNL	±0.5 LSB - guarantees monotonic transfer function and absence of missing codes in production units.
Power Dissipation	80 mW at 3 V - enables portable, battery-sensitive applications; drops to <4 mW in STBY mode.
Input Bandwidth	300 MHz (–3 dB) - allows direct sampling of wideband RF/IF signals without external pre-filtering.
Aperture Jitter	2 ps RMS - limits SNR degradation to <0.5 dB at 100 MHz input, critical for undersampling fidelity.

Pinout & Package

AD9200JRSZ is housed in a 28-lead Shrink Small Outline Package (SSOP), RoHS-compliant, with 0.65 mm lead pitch and exposed pad not connected internally. Thermal resistance θ_JA = 120°C/W (JEDEC standard board).

Pin	Circuit Role	Design Meaning
1	AVSS	Analog ground reference - must be isolated from digital ground and tied to low-impedance analog return plane.
2	DRVDD	Digital output driver supply - independent of AVDD; sets logic swing (3 V or 5 V) for D0–D9 and OTR outputs.
3–12	D0–D9	Parallel straight-binary data outputs - MSB = D9, LSB = D0; three-state controlled by THREE-STATE pin.
13	OTR	Out-of-range indicator - asserts high when AIN exceeds REFTS or falls below REFBS; used with D9 for overflow polarity detection.
14	DRVSS	Digital ground - separate from AVSS; required for clean digital output switching and noise isolation.
15	CLK	Asynchronous sampling clock input - 20 MHz nominal; minimum pulse width 22.5 ns; initiates pipeline conversion cycle.
16	THREE-STATE	Output enable control - logic high places D0–D9 and OTR in high-impedance state; essential for bus sharing.
17	STBY	Power-down control - logic high disables internal bias and clocks, reducing consumption to <4 mW.
18	REFSENSE	Reference configuration select - tied to AVDD for external reference; to GND for 2 V internal; to VREF for 1 V internal.
19	CLAMP	Clamp enable - active-high signal that closes internal switch to servo AIN to CLAMPIN voltage (ARS/KST only).
20	CLAMPIN	Clamp reference input - accepts 0.5 V–2.7 V DC level; sets restored DC offset for AC-coupled video inputs.
21	REFTS	Top reference sense - defines upper bound of input range; driven externally or sourced from internal VREF.
22	REFTF	Top reference force - decoupled with 0.1 µF capacitor; connects to internal reference buffer output.
23	MODE	Input configuration mode - set to AVDD for top/bottom single-ended; AVDD/2 for center-span or differential operation.
24	REFBF	Bottom reference force - decoupled with 0.1 µF capacitor; complements REFTF for stable reference buffering.
25	REFBS	Bottom reference sense - defines lower bound of input range; grounded for 0–1 V span or set to offset voltage.
26	VREF	Internal reference output - provides 1 V or 2 V depending on REFSENSE connection; bypassed with 1 µF + 0.1 µF.
27	AIN	Analog input - switched-capacitor node with 1 pF capacitance; supports DC-coupled or AC-coupled (clamped) drive.
28	AVDD	Analog supply - powers core ADC, SHA, and reference; must be filtered separately from DRVDD and AVSS.

Key Features

Feature	Design Value
Pin-compatible upgrade path	Direct replacement for AD876 in existing sockets - enables migration to lower supply voltages (2.7–5.5 V) without PCB change.
Configurable input topology	Four modes via MODE/REFSENSE: single-ended top/bottom, center-span, differential, or AD876 legacy - supports imaging, comms, and instrumentation.
On-chip clamp circuit	DC restoration for AC-coupled video (NTSC/PAL); enabled in AD9200ARS/AD9200KST variants - eliminates external clamping ICs.
Low-power pipeline architecture	80 mW at 20 MSPS, <4 mW in STBY - reduces thermal load and extends battery life in portable test equipment and SDR front-ends.
Flexible reference system	Internal 1 V/2 V bandgap or external reference (up to 2 V p-p span); REFTF/REFBF decoupling ensures <100 µV noise contribution.

Applications

Communications Receiver Front-End	Digital Video Digitization
Use Scenario: Sampling IF signals at 70 MHz in a software-defined radio receiver with undersampling architecture. IC Role / Device Role / Timing Role: ADC core capturing 20 MSPS complex baseband samples; OTR monitors signal clipping during AGC transients. Use Value: 300 MHz input bandwidth and 2 ps aperture jitter preserve SFDR >61 dB, enabling clean channel separation in crowded spectrum.	Use Scenario: Digitizing composite NTSC video signals in broadcast-grade capture cards with DC restoration. IC Role / Device Role / Timing Role: High-fidelity 10-bit sampling at 13.5 MHz pixel clock; CLAMP/CLAMPIN pins restore blanking-level DC reference. Use Value: Built-in clamp (in ARS/KST variants) eliminates need for external op-amp clamping circuit, reducing BOM count and layout area.
Portable Test Instrumentation	Industrial Imaging System
Use Scenario: Battery-powered oscilloscope module requiring low power, wide dynamic range, and fast wake-up from sleep. IC Role / Device Role / Timing Role: Primary acquisition ADC; STBY pin enables sub-4 mW standby between triggered acquisitions. Use Value: 54.5 dB SINAD at 3.58 MHz and 80 mW total power allow >8-bit ENOB performance within strict thermal and energy budgets.	Use Scenario: High-speed line-scan camera digitizing 10-bit grayscale output from CCD sensors at 20 MHz pixel rate. IC Role / Device Role / Timing Role: Parallel-output ADC interfacing directly to FPGA image buffer; THREE-STATE enables shared data bus with other peripherals. Use Value: Guaranteed no-missing-codes and ±0.5 LSB DNL ensure accurate intensity representation across full temperature range (–40°C to +85°C).

Communications Receiver Front-End

Digital Video Digitization

Use Scenario: Sampling IF signals at 70 MHz in a software-defined radio receiver with undersampling architecture.

IC Role / Device Role / Timing Role: ADC core capturing 20 MSPS complex baseband samples; OTR monitors signal clipping during AGC transients.

Use Value: 300 MHz input bandwidth and 2 ps aperture jitter preserve SFDR >61 dB, enabling clean channel separation in crowded spectrum.

Use Scenario: Digitizing composite NTSC video signals in broadcast-grade capture cards with DC restoration.

IC Role / Device Role / Timing Role: High-fidelity 10-bit sampling at 13.5 MHz pixel clock; CLAMP/CLAMPIN pins restore blanking-level DC reference.

Use Value: Built-in clamp (in ARS/KST variants) eliminates need for external op-amp clamping circuit, reducing BOM count and layout area.

Portable Test Instrumentation

Industrial Imaging System

Use Scenario: Battery-powered oscilloscope module requiring low power, wide dynamic range, and fast wake-up from sleep.

IC Role / Device Role / Timing Role: Primary acquisition ADC; STBY pin enables sub-4 mW standby between triggered acquisitions.

Use Value: 54.5 dB SINAD at 3.58 MHz and 80 mW total power allow >8-bit ENOB performance within strict thermal and energy budgets.

Use Scenario: High-speed line-scan camera digitizing 10-bit grayscale output from CCD sensors at 20 MHz pixel rate.

IC Role / Device Role / Timing Role: Parallel-output ADC interfacing directly to FPGA image buffer; THREE-STATE enables shared data bus with other peripherals.

Use Value: Guaranteed no-missing-codes and ±0.5 LSB DNL ensure accurate intensity representation across full temperature range (–40°C to +85°C).

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit, 20 MSPS ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9203ARUZ	10-bit, 40 MSPS; 3.3 V only; no internal reference; requires external REFIO; smaller 28-lead TSSOP.	Higher speed but lacks integrated clamp and programmable reference; suited for FPGA-based systems with external ref management.	Select AD9203ARUZ when sampling rate >20 MSPS is required and external reference infrastructure already exists.
MAX1186ETL+	10-bit, 20 MSPS; 3 V supply; integrated reference; SPI-configurable; 40-lead TQFN; no clamp function.	Serial interface reduces pin count but adds latency; lacks OTR and three-state outputs; unsuitable for parallel-bus video systems.	Select MAX1186ETL+ for space-constrained designs where serial interface and small footprint outweigh parallel output needs.

Compared with AD9200JRSZ, AD9203ARUZ offers double the sampling rate but removes on-chip reference and clamp functionality, increasing system complexity. MAX1186ETL+ saves board area via serial interface but sacrifices real-time parallel throughput and overflow monitoring - making AD9200JRSZ optimal for video digitization and IF undersampling where deterministic timing and integrated features matter.

Availability

AD9200JRSZ is available at Aetrix Electronics and suitable for communications receiver front-ends, digital video digitization, and portable test instrumentation requiring stable component supply, long-term industrial temperature support (–40°C to +85°C), and pin-compatible legacy migration paths.

Supply support for AD9200JRSZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9200JRSZ belongs to Analog Devices' precision high-speed ADC product line, designed specifically for cost-sensitive, low-power applications in communications, video, and instrumentation where integration, reliability, and ease of use are critical.

FAQ

What is the operating temperature range for the AD9200JRSZ?

The AD9200JRSZ is specified for the industrial temperature range of –40°C to +85°C. This rating applies to all electrical specifications in the datasheet unless otherwise noted, and is validated across the full 28-lead SSOP package. The AD9200JRSZ maintains ±0.5 LSB DNL and 54.5 dB SINAD performance across this range, making it suitable for outdoor base stations and factory-floor imaging systems. No derating is required within these limits.

Does the AD9200JRSZ include an on-chip sample-and-hold amplifier?

Yes, the AD9200JRSZ integrates a high-bandwidth sample-and-hold (SHA) amplifier optimized for 300 MHz input bandwidth and 2 ps aperture jitter. This SHA supports both multiplexed multi-channel systems and single-channel high-frequency sampling up to and beyond the Nyquist rate. Its switched-capacitor input presents 1 pF capacitance and 50 kΩ effective resistance at 20 MSPS, simplifying drive requirements compared to external SHA solutions.

Can the AD9200JRSZ operate with a 5 V supply?

Yes, the AD9200JRSZ supports analog supply (AVDD) and digital driver supply (DRVDD) from 2.7 V to 5.5 V. At 5 V, digital outputs deliver VOH ≥ +4.5 V (IOH = 50 µA) and VOL ≤ +0.4 V (IOL = 1.6 mA), ensuring TTL/CMOS compatibility. Power dissipation increases to ~100 mW, and dynamic performance remains consistent - SINAD stays ≥54 dB at 10 MHz input. All absolute maximum ratings and functional specs remain valid across the full voltage range.

Is the clamp function available on the AD9200JRSZ?

No, the clamp function is not available on the AD9200JRSZ. It is only implemented in the AD9200ARS and AD9200KST variants (48-lead LQFP packages). The AD9200JRSZ shares the same pinout and core ADC functionality but omits the CLAMP and CLAMPIN pins and associated internal circuitry. For DC restoration in video applications, users must select AD9200ARS or AD9200KST, or implement external clamping with a precision op-amp and switch.

What is the pipeline latency of the AD9200JRSZ?

The AD9200JRSZ has a fixed pipeline latency of 3 clock cycles. When a rising edge arrives at the CLK pin, the corresponding digital output data for that sample appears on D0–D9 after exactly three subsequent CLK edges. This deterministic delay enables precise timing alignment in FPGA-based capture engines and simplifies synchronization with downstream DSP blocks. Latency is independent of input frequency, reference configuration, or power mode.

AD9200JRSZ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 28-SSOP (0.209", 5.30mm Width)

Packaging:: Tube

Product Status:: Active

Number of Bits:: 10

Sampling Rate (Per Second):: 20M

Number of Inputs:: 1

Input Type:: Differential, Single Ended

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 2.7V ~ 5.5V

Voltage - Supply, Digital:: 2.7V ~ 5.5V

Features:: -

Operating Temperature:: 0°C ~ 70°C

Supplier Device Package:: 28-SSOP

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD9200JRSZ FAQ

1.How can I place an order for AD9200JRSZ through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9200JRSZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9200JRSZ reliable?

The price and inventory of AD9200JRSZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9200JRSZ is usually 5 days.

3.What payment methods are accepted for AD9200JRSZ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9200JRSZ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9200JRSZ?

AD9200JRSZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9200JRSZ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9200JRSZ?

For technical support, including AD9200JRSZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9200JRSZ requirements.

6.How does Aetrix verify that AD9200JRSZ is sourced from the original manufacturer or authorized distributors?

All AD9200JRSZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9200JRSZ meets industry standards.

7.What is the process for return or replacement of AD9200JRSZ?

All AD9200JRSZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9200JRSZ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9200JRSZ part is unused and in its original packaging.

Return procedure for AD9200JRSZ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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