Analog Devices Inc. AD9226ARSRL
- Part No.:
- AD9226ARSRL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
AD9226ARSRL.pdf
- Description:
- IC ADC 12BIT PIPELINED 28SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,740
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Product details
Overview
AD9226ARSRL from Analog Devices is a monolithic, single-supply 12-bit, 65 MSPS analog-to-digital converter with on-chip sample-and-hold amplifier and voltage reference. It delivers 69 dB SNR at 31 MHz input, 85 dB SFDR, and ±0.6 LSB INL/DNL, enabling high-fidelity IF undersampling in communications receivers and imaging front-ends.
For engineers reviewing the AD9226ARSRL datasheet, AD9226ARSRL pinout, AD9226ARSRL application, or AD9226ARSRL equivalent, key selection considerations include its 750 MHz analog input bandwidth, clock duty cycle stabilizer, differential or single-ended input flexibility, 28-lead SSOP package, and guaranteed no missing codes over –40°C to +85°C.
Technical Context
The AD9226ARSRL employs a nine-stage, 1½-bit-per-stage pipelined architecture with on-chip correction logic and a patented wideband sample-and-hold amplifier. Its SHA supports full-power bandwidth up to 750 MHz and maintains outstanding AC performance through 300 MHz input frequencies.
It features dual-mode operation: programmable data format (straight binary or two's complement) and clock duty cycle stabilization. The internal 1 V/2 V reference is user-selectable via SENSE pin, and external reference support enables system-level precision tuning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees 4096 discrete output levels with no missing codes across full temperature range. |
| Sampling Rate | 65 MSPS - supports Nyquist-limited signal capture up to 32.5 MHz or IF undersampling beyond 100 MHz. |
| SNR @ 31 MHz | 69 dBc - enables >11-bit effective resolution for medium-bandwidth RF/IF digitization. |
| SFDR @ 31 MHz | 85 dBc - suppresses spurious tones sufficiently for demanding spectral purity applications like WCDMA. |
| INL / DNL | ±0.6 LSB - ensures monotonicity and linearity critical for closed-loop control and measurement systems. |
| Analog Input BW | 750 MHz - allows direct sampling of high-frequency IF signals without external amplification or filtering. |
| Power Dissipation | 475 mW - achieves high-speed ADC performance with single 5 V AVDD and 3 V DRVDD supplies. |
Pinout & Package
AD9226ARSRL is packaged in a 28-lead Shrink Small Outline Package (SSOP), RoHS-compliant, with 0.65 mm lead pitch and exposed thermal pad (not electrically connected). Pin 1 identifier is marked by a dot or notch.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | CLK | Single-ended clock input; rising edge triggers conversion; duty cycle stabilizer active when MODE tied to AVDD or ground. |
| 2 | BIT 12 (LSB) | Least significant output bit; CMOS-compatible, driven by 3 V/5 V DRVDD supply. |
| 3–12 | BITS 11–2 | Parallel digital output bits; three-state controlled by OEB; timing-critical for high-speed interface design. |
| 13 | BIT 1 (MSB) | Most significant output bit; polarity indicates overflow when combined with OTR signal. |
| 14 | OTR | Out-of-range flag; asserts high when input exceeds ±VREF/2, enabling real-time clipping detection. |
| 15, 26 | AVDD | 5 V analog supply; must be decoupled locally with 0.1 µF ceramic + 10 µF tantalum per supply pin. |
| 16, 25 | AVSS | Analog ground; separate from digital ground (DRVSS); requires low-impedance star connection. |
| 17 | SENSE | Reference select input; logic high selects internal 2 V reference, low selects 1 V mode. |
| 18 | VREF | Reference I/O pin; outputs selected internal reference or accepts external 1 V/2 V source. |
| 19 | REFCOM (AVSS) | Reference common; connects to AVSS; establishes reference midpoint for differential input configuration. |
| 20, 21 | CAPB, CAPT | Noise reduction pins; require 15 pF capacitors to AVSS to stabilize internal reference and reduce switching noise. |
| 22 | MODE | Data format/clock stabilizer control; high = two's complement, low = straight binary; also enables duty cycle correction. |
| 23, 24 | VINA, VINB | Differential analog inputs; interchangeable but reversal inverts output data; support ac/dc coupling and 1 V or 2 V p-p spans. |
| 27 | DRVSS | Digital output driver ground; must be isolated from AVSS to prevent digital noise coupling into analog path. |
| 28 | DRVDD | 3 V to 5 V digital output supply; sets logic swing for parallel data bus; enables interfacing with mixed-voltage systems. |
Key Features
| Feature | Design Value |
|---|---|
| Patented on-chip sample-and-hold | 750 MHz full-power bandwidth enables direct IF sampling up to 300 MHz without external amplifiers. |
| Programmable internal voltage reference | Selectable 1 V or 2 V output via SENSE pin; eliminates need for external reference in cost-sensitive designs. |
| Integrated clock duty cycle stabilizer | Removes sensitivity to clock asymmetry-critical for stable performance with FPGA or ASIC-generated clocks. |
| Flexible analog input interface | Supports both differential and single-ended configurations with matched impedance requirements for optimal SNR/THD. |
| Guaranteed no missing codes | Ensures monotonic transfer function across –40°C to +85°C-essential for precision measurement and control loops. |
Applications
| Communications IF Receiver | Medical Ultrasound Digitizer |
|---|---|
|
Use Scenario: Digitizing 70 MHz IF signals from satellite downconverters in software-defined radio base stations. IC Role / Device Role / Timing Role: High-speed ADC capturing intermediate frequency samples for digital downconversion and demodulation. Use Value: 85 dB SFDR prevents adjacent-channel interference; 750 MHz input bandwidth avoids external amplification before sampling. |
Use Scenario: Sampling echo return signals from phased-array transducers operating at 5–15 MHz center frequencies. IC Role / Device Role / Timing Role: Precision front-end ADC converting analog beamformed echoes into digital domain for real-time image reconstruction. Use Value: ±0.6 LSB INL preserves spatial resolution; no missing codes ensures accurate amplitude mapping for B-mode imaging. |
| Test & Measurement Digitizer | Radar Signal Acquisition |
|
Use Scenario: Capturing transient waveforms in automated test equipment requiring 12-bit fidelity and 65 MSPS throughput. IC Role / Device Role / Timing Role: Core sampling engine synchronizing to external trigger and clock sources for time-domain analysis. Use Value: 69 dB SNR enables sub-12-bit ENOB at 31 MHz; clock stabilizer tolerates jitter-prone system clocks. |
Use Scenario: Acquiring pulsed L-band radar returns (1–2 GHz IF) in electronic warfare receivers using undersampling techniques. IC Role / Device Role / Timing Role: Wideband ADC performing bandpass sampling of high-frequency IF signals without local oscillator complexity. Use Value: 300 MHz usable input frequency range and 82 dB SFDR at 60 MHz support clean pulse detection in dense RF environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9225ARS | 12-bit, 50 MSPS; lower power (320 mW); same 28-lead SSOP package and pinout. | Lower sampling rate limits IF bandwidth to ~25 MHz; suitable for cost-optimized, lower-bandwidth comms systems. | Choose AD9225ARS where 50 MSPS suffices and power budget is tighter; drop-in replacement with no layout change. |
| ADS5463IPFP | 13-bit, 500 MSPS; 0.9 V core supply; 80-lead HTQFP; higher ENOB (7.8 bits @ 250 MHz). | Targets ultra-wideband radar and high-end instrumentation; requires more complex power sequencing and layout. | Choose ADS5463IPFP when >100 MHz instantaneous bandwidth or >12-bit ENOB at high IF is required; not pin-compatible. |
Compared with AD9225ARS and ADS5463IPFP, the AD9226ARSRL uniquely balances 65 MSPS speed, 12-bit accuracy, 750 MHz analog bandwidth, and SSOP packaging-making it optimal for mid-tier IF sampling where board space, power, and performance intersect.
Availability
AD9226ARSRL is available at Aetrix Electronics and suitable for communications infrastructure, medical ultrasound systems, and test equipment requiring stable component supply with industrial temperature range (–40°C to +85°C) and long-term availability.
Supply support for AD9226ARSRL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD9226 belongs to Analog Devices' high-speed data converter product line, designed specifically for demanding IF sampling, communications receiver, and imaging applications requiring precision, speed, and low power in compact packages.
FAQ
What is the maximum analog input frequency supported by the AD9226ARSRL?
The AD9226ARSRL features a 750 MHz full-power analog input bandwidth, verified by characterization up to 300 MHz with maintained AC performance. While usable for bandpass sampling beyond Nyquist, its specified SFDR and SNR degrade above 200 MHz; for reliable IF undersampling, inputs up to 140 MHz are documented with 65 dBc SNR and 60 dBc SFDR in typical conditions.
Does the AD9226ARSRL require an external reference, or does it have an internal one?
The AD9226ARSRL includes a factory-trimmed, programmable internal voltage reference delivering either 1 V or 2 V, selected via the SENSE pin. External reference is optional and supported on the VREF pin-enabling system-level calibration or improved stability when paired with a precision external source. No external reference is required for standard operation.
How does the clock duty cycle stabilizer in the AD9226ARSRL improve system robustness?
The AD9226ARSRL's integrated clock duty cycle stabilizer corrects asymmetric clock waveforms internally, eliminating sensitivity to duty cycle variations outside the 40–60% range. This allows reliable operation with clocks generated by FPGAs, PLLs, or dividers that may exhibit jitter or asymmetry-reducing SNR degradation and simplifying clock tree design without external duty cycle correction circuits.
Is the AD9226ARSRL pin-compatible with other members of the AD922x family?
Yes, the AD9226ARSRL in 28-lead SSOP is pin-compatible with AD9220, AD9221, AD9223, AD9224, and AD9225-sharing identical pin functions, power domains, and interface timing. This enables drop-in upgrades from lower-speed variants (e.g., AD9225ARS at 50 MSPS) without PCB revision, provided layout accommodates the AD9226ARSRL's slightly higher power dissipation.
What are the recommended decoupling practices for the AD9226ARSRL's AVDD and DRVDD supplies?
Each AVDD pin (pins 15, 26) requires local decoupling with a 0.1 µF X7R ceramic capacitor placed within 2 mm, plus a bulk 10 µF tantalum or polymer capacitor nearby. DRVDD (pin 28) needs a dedicated 0.1 µF ceramic capacitor. AVSS and DRVSS grounds must be separated and joined at a single point near the device; all decoupling capacitors must reference their respective ground planes directly.
AD9226ARSRL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 65M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 2.85V ~ 5.25V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9226ARSRL FAQ
1.How can I place an order for AD9226ARSRL through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9226ARSRL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9226ARSRL reliable?
The price and inventory of AD9226ARSRL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9226ARSRL is usually 5 days.
3.What payment methods are accepted for AD9226ARSRL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9226ARSRL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9226ARSRL?
AD9226ARSRL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9226ARSRL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9226ARSRL?
For technical support, including AD9226ARSRL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9226ARSRL requirements.
6.How does Aetrix verify that AD9226ARSRL is sourced from the original manufacturer or authorized distributors?
All AD9226ARSRL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9226ARSRL meets industry standards.
7.What is the process for return or replacement of AD9226ARSRL?
All AD9226ARSRL units undergo pre-shipment inspection (PSI). If there is an issue with AD9226ARSRL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9226ARSRL part is unused and in its original packaging.
Return procedure for AD9226ARSRL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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