Analog Devices Inc. AD9235BRU-40
- Part No.:
- AD9235BRU-40
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AD9235BRU-40.pdf
- Description:
- IC ADC 12BIT PIPELINED 28TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD9235BRU-40 from Analog Devices is a 12-bit, 40 MSPS monolithic analog-to-digital converter (ADC) operating from a single 3 V supply (2.7 V to 3.6 V), featuring a differential sample-and-hold amplifier (SHA), on-chip voltage reference, and clock duty cycle stabilizer. It delivers 70 dBc SNR and 85 dBc SFDR at Nyquist with 2 Vp-p differential input, and supports flexible input ranges (1 Vp-p or 2 Vp-p) for IF sampling in communications receivers and ultrasound front-ends.
For engineers reviewing the AD9235BRU-40 datasheet, AD9235BRU-40 pinout, AD9235BRU-40 application, or AD9235BRU-40 equivalent, this page provides verified technical context, real-world use cases, validated alternatives, and supply-chain support for industrial and medical signal acquisition systems requiring stable 40 MSPS sampling performance.
Technical Context
The AD9235BRU-40 employs a multistage differential pipelined architecture with output error correction logic to guarantee 12-bit accuracy and no missing codes across –40°C to +85°C. Its wide-bandwidth SHA supports up to 100 MHz analog input frequencies and configurable single-ended or differential operation.
It integrates a programmable internal voltage reference (0.5 V or 1.0 V mode), digital output driver supply (DRVDD) decoupled separately for 2.5 V/3.3 V logic compatibility, and an out-of-range (OTR) flag for overflow detection. The clock duty cycle stabilizer ensures robust timing performance despite input clock asymmetry - though DCS is disabled in the -40 variant per datasheet Table 3 footnote.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees 4096 distinct output codes with no missing codes over full temperature range. |
| Sampling Rate | 40 MSPS - fixed maximum conversion rate; supports minimum 1 MSPS for low-power operation. |
| SNR @ 40 MSPS | 70 dBc to Nyquist - enables high-fidelity digitization of IF signals up to 20 MHz without significant quantization noise degradation. |
| SFDR @ 40 MSPS | 85 dBc to Nyquist - suppresses spurious tones critical for CDMA-One and IS-95 baseband recovery. |
| Power Consumption | 165 mW DC input @ 40 MSPS - low power enables battery-powered handheld scopemeters and portable ultrasound. |
| Analog Input Bandwidth | 500 MHz - supports undersampling of RF/IF signals beyond Nyquist, e.g., direct IF sampling at 70 MHz. |
| Differential Nonlinearity | ±0.35 LSB typ - ensures monotonic transfer function essential for closed-loop control and precision measurement. |
| Input Voltage Range | 1 Vp-p or 2 Vp-p differential - selectable via VREF/SENSE pins to match signal chain gain and noise floor. |
Pinout & Package
AD9235BRU-40 is packaged in a 28-lead TSSOP (RU-28) with exposed paddle soldered to ground plane for thermal and EMI performance. Pin functions are electrically identical to the LFCSP variant but mapped to 28 pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK | Clock Input | Single-ended CMOS-compatible input controlling all conversion cycles; requires external termination for impedance matching. |
| VIN+, VIN– | Differential Analog Input | High-bandwidth (500 MHz) inputs accepting 1 Vp-p or 2 Vp-p differential signals; common-mode range referenced to AVDD/2. |
| D0–D11 | Parallel Digital Output | 12-bit straight binary or twos complement data bus; outputs driven by DRVDD-supplied buffers compatible with 2.5 V or 3.3 V logic. |
| OTR | Out-of-Range Flag | Active-high signal indicating input exceeds selected full-scale range; used with MSB to distinguish high/low overflow. |
| MODE | Data Format & DCS Control | Selects offset binary/twos complement output format; DCS function is inactive in AD9235BRU-40 per datasheet Table 3. |
| SENSE, VREF | Reference Configuration | SENSE selects 0.5 V or 1.0 V internal reference; VREF is reference input/output node - bypassed externally for stability. |
| AVDD, AGND | Analog Power/Ground | 3 V analog supply with separate ground plane; requires low-ESR decoupling (0.1 µF + 10 µF) near AVDD pin. |
| DRVDD, DGND | Digital Driver Supply | Independent 2.25–3.6 V supply for output buffers; decoupled to DGND to isolate digital switching noise from analog section. |
Key Features
| Feature | Design Value |
|---|---|
| Single 3 V supply operation | Eliminates dual-supply design complexity while maintaining 12-bit linearity and <70 dBc SNR at 40 MSPS. |
| Differential input with 500 MHz bandwidth | Enables direct undersampling of 70 MHz IF signals in CDMA receivers without external anti-alias filtering. |
| On-chip reference and SHA | Reduces BOM count and layout area; eliminates need for external reference IC and discrete track-and-hold circuitry. |
| Flexible analog input range (1 Vp-p/2 Vp-p) | Allows optimization of dynamic range vs. noise floor - e.g., 2 Vp-p for high-SNR ultrasound beamforming, 1 Vp-p for low-voltage sensor interfaces. |
| Offset binary or twos complement output format | Supports seamless integration with FPGA-based DSP pipelines (offset binary) or signed arithmetic processors (twos complement). |
| Out-of-range (OTR) indicator | Provides real-time saturation detection for automatic gain control (AGC) loops in medical imaging and spectrum analyzers. |
Applications
| Ultrasound Beamforming | CDMA Baseband Receiver |
|---|---|
|
Use Scenario: Digitizing echo return signals from phased-array transducers at 20–40 MSPS for real-time beam synthesis. IC Role / Device Role / Timing Role: High-speed ADC capturing time-aligned RF samples from multiple channels with matched latency (7-cycle pipeline delay). Use Value: 70 dBc SNR preserves weak tissue boundary reflections; 12-bit resolution enables >70 dB dynamic range required for Doppler velocity estimation. |
Use Scenario: IF sampling of 45 MHz CDMA-One intermediate frequency in cellular base station receivers. IC Role / Device Role / Timing Role: Direct-conversion ADC converting band-limited IF to digital domain with minimal front-end filtering. Use Value: 500 MHz analog input bandwidth allows alias-free sampling of 45 MHz IF; 85 dBc SFDR suppresses adjacent-channel interference. |
| Handheld Scopemeter | Battery-Powered Spectrum Analyzer |
|
Use Scenario: Portable oscilloscope capturing transient waveforms up to 20 MHz bandwidth with 40 MSPS sampling. IC Role / Device Role / Timing Role: Core digitizer providing 12-bit waveform fidelity and low-latency parallel output for real-time display buffering. Use Value: 165 mW power consumption extends battery life; single 3 V supply simplifies power management in compact enclosures. |
Use Scenario: Field-deployable RF analyzer measuring spectral occupancy from 1 MHz to 100 MHz using undersampling techniques. IC Role / Device Role / Timing Role: Wideband ADC enabling harmonic-rich input capture with calibrated amplitude response up to Nyquist. Use Value: Guaranteed no missing codes ensures accurate amplitude histogramming; ±0.35 LSB DNL prevents distortion in FFT-based measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit, 40 MSPS ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9235BCP-40 | LFCSP-32 package (vs. TSSOP-28); lower θJA (32.5°C/W vs. 67.7°C/W); identical electrical specs and pinout mapping. | Better thermal performance in high-density PCBs; requires different footprint and reflow profile. | Select AD9235BCP-40 for space-constrained, thermally demanding designs; AD9235BRU-40 preferred for legacy TSSOP layouts and cost-sensitive production. |
| ADS5272IPFP | Texas Instruments 12-bit, 40 MSPS ADC; 72 dBc SNR (vs. 70 dBc); LVDS outputs (vs. CMOS); no integrated reference. | Requires external reference and level-shifting; superior SNR suits high-fidelity test equipment. | Choose ADS5272IPFP when system-level SNR >71 dBc is mandatory and LVDS interface is already present; AD9235BRU-40 offers simpler integration with on-chip reference and CMOS outputs. |
Compared with AD9235BCP-40, AD9235BRU-40 trades thermal efficiency for lower assembly cost and broader distributor availability in TSSOP; versus ADS5272IPFP, it delivers faster time-to-design via integrated reference and CMOS compatibility, at the expense of 2 dB SNR and absence of LVDS noise immunity.
Availability
AD9235BRU-40 is available at Aetrix Electronics and suitable for ultrasound beamforming, CDMA baseband receivers, and handheld scopemeters requiring stable component supply with guaranteed long-term manufacturability.
Supply support for AD9235BRU-40 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.
The AD9235 family was designed specifically for cost-sensitive, power-efficient signal acquisition in communications, medical imaging, and portable instrumentation - delivering 12-bit precision at 20/40/65 MSPS with single-supply simplicity.
FAQ
What is the maximum analog input frequency supported by AD9235BRU-40?
The AD9235BRU-40 features a 500 MHz analog input bandwidth, enabling reliable undersampling of signals up to 100 MHz while maintaining specified SNR and SFDR performance. At 40 MSPS, its Nyquist frequency is 20 MHz, but the wide SHA bandwidth permits direct IF sampling of higher-frequency signals such as 45 MHz CDMA channels without external amplification or filtering.
Does AD9235BRU-40 include an internal voltage reference?
Yes, AD9235BRU-40 integrates a precision internal voltage reference configurable for either 0.5 V or 1.0 V output via the SENSE pin. In 1.0 V mode, it supports 2 Vp-p differential input range; in 0.5 V mode, it enables 1 Vp-p range. External bypassing of VREF is required for optimal stability and noise performance.
Is the clock duty cycle stabilizer (DCS) active in AD9235BRU-40?
No, the clock duty cycle stabilizer is not active in AD9235BRU-40. Per the AD9235 Rev. D datasheet Table 3 footnote, DCS functionality applies only to the AD9235BRU/BCP-65 variant. For AD9235BRU-40, the CLK input must meet specified pulse-width requirements (min 8.8 ns high/low) without DCS compensation.
What digital output formats does AD9235BRU-40 support?
AD9235BRU-40 supports both offset binary and twos complement output formats, selected via the MODE pin. Offset binary is commonly used in FPGA-based data capture systems for unsigned arithmetic, while twos complement simplifies signed math in DSP processors. Both formats deliver full 12-bit resolution with identical timing and drive strength.
How is the out-of-range (OTR) signal used in AD9235BRU-40?
The OTR signal in AD9235BRU-40 is an active-high flag indicating analog input has exceeded the selected full-scale range. When combined with the MSB (D11), it distinguishes between high overflow (OTR = 1, D11 = 1) and low overflow (OTR = 1, D11 = 0), enabling precise automatic gain control (AGC) and signal clipping detection in real-time ultrasound and spectrum analysis applications.
AD9235BRU-40 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 40M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.25V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9235BRU-40 FAQ
1.How can I place an order for AD9235BRU-40 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9235BRU-40 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9235BRU-40 reliable?
The price and inventory of AD9235BRU-40 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9235BRU-40 is usually 5 days.
3.What payment methods are accepted for AD9235BRU-40?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9235BRU-40 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9235BRU-40?
AD9235BRU-40 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9235BRU-40 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9235BRU-40?
For technical support, including AD9235BRU-40 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9235BRU-40 requirements.
6.How does Aetrix verify that AD9235BRU-40 is sourced from the original manufacturer or authorized distributors?
All AD9235BRU-40 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9235BRU-40 meets industry standards.
7.What is the process for return or replacement of AD9235BRU-40?
All AD9235BRU-40 units undergo pre-shipment inspection (PSI). If there is an issue with AD9235BRU-40, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9235BRU-40 part is unused and in its original packaging.
Return procedure for AD9235BRU-40:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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