Analog Devices Inc. AD9235BRUZ-40
- Part No.:
- AD9235BRUZ-40
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AD9235BRUZ-40.pdf
- Description:
- IC ADC 12BIT PIPELINED 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:244
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD9235BRUZ-40 from Analog Devices is a 12-bit, 40 MSPS monolithic analog-to-digital converter (ADC) operating from a single 3 V supply (2.7 V to 3.6 V). It features a differential sample-and-hold amplifier with 500 MHz input bandwidth, on-chip reference, and clock duty cycle stabilizer - enabling high-fidelity IF sampling in communications receivers and ultrasound front-ends.
For engineers reviewing the AD9235BRUZ-40 datasheet, AD9235BRUZ-40 pinout, AD9235BRUZ-40 application, or AD9235BRUZ-40 equivalent, this page delivers verified specifications including SNR = 70.4 dBc at Nyquist, SFDR = 85 dBc, DNL = ±0.35 LSB, 28-lead TSSOP package, and industrial temperature range (–40°C to +85°C).
Technical Context
The AD9235BRUZ-40 implements a multistage differential pipelined architecture with output error correction logic, guaranteeing no missing codes across its full operating temperature range. Its SHA supports flexible analog input configurations - including user-selectable 1 Vp-p or 2 Vp-p differential ranges - and maintains performance up to 100 MHz input frequency.
A dedicated clock duty cycle stabilizer (DCS) compensates for wide variations in input clock pulse width while preserving AC performance; digital outputs are configurable as offset binary or twos complement, with OTR (out-of-range) flag signaling overflow conditions relative to the selected input span.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees 4096 distinct output codes with no missing codes over full temperature range. |
| Sampling Rate | 40 MSPS - supports real-time digitization of IF signals up to 20 MHz (Nyquist), suitable for CDMA-One and IS-95 baseband processing. |
| SNR / SFDR | 70.4 dBc / 85 dBc at Nyquist - enables high dynamic range signal capture in ultrasound beamforming and spectrum monitoring. |
| Power Consumption | 165 mW at 40 MSPS - low power enables battery-powered instruments and handheld scopemeters without thermal derating. |
| Analog Input Bandwidth | 500 MHz - allows undersampling of RF/IF signals beyond Nyquist, supporting direct IF sampling architectures. |
| Differential Nonlinearity | ±0.35 LSB (typ) - ensures monotonic transfer function critical for closed-loop control and precision measurement systems. |
| Input Voltage Range | 1 Vp-p or 2 Vp-p differential - selectable via VREF configuration, simplifying interface to variable-gain amplifiers and mixers. |
Pinout & Package
The AD9235BRUZ-40 is housed in a 28-lead TSSOP (Thin Shrink Small Outline Package) with exposed paddle, optimized for thermal dissipation and industrial PCB assembly. Pin 1 is OTR (Out-of-Range indicator); pins 15–22 and 25–28 carry D0 (LSB) through D11 (MSB) data outputs.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| OTR (Pin 1) | Overflow flag output | Asserts high when input exceeds ±FSR/2; used with MSB to distinguish low/high saturation in real-time signal processing. |
| MODE (Pin 2) | Data format & DCS control | Selects offset binary/twos complement output and enables/disables clock duty cycle stabilizer for timing robustness. |
| SENSE (Pin 3) | Reference mode selection | Configures internal reference (1.0 V or 0.5 V) and determines input span (2 Vp-p or 1 Vp-p differential). |
| VIN+, VIN– (Pins 9, 10) | Differential analog inputs | High-impedance, 7 pF input capacitance nodes accepting true differential signals up to 100 MHz without external termination. |
| CLK (Pin 13) | Master sampling clock input | Single-ended CMOS-compatible input; DCS circuit tolerates 30%–70% duty cycle variation at 40 MSPS. |
| PDWN (Pin 14) | Power-down enable | Active-high signal reduces power to 1.0 mW; wake-up time is 3.0 ms with standard 0.1 µF/10 µF decoupling. |
| D0–D11 (Pins 15–22, 25–28) | Parallel digital outputs | 12-bit LVCMOS outputs referenced to DRVDD (2.25 V–3.6 V), supporting 2.5 V or 3.3 V logic families. |
Key Features
| Feature | Design Value |
|---|---|
| Single 3 V supply operation | Eliminates dual-supply design complexity and reduces BOM count; AVDD (2.7–3.6 V) and DRVDD (2.25–3.6 V) are independently decoupled. |
| On-chip voltage reference | 1.0 V or 0.5 V selectable reference with ±5 mV output error (1 V mode), removing need for external precision reference ICs. |
| Flexible analog input range | Supports both 1 Vp-p and 2 Vp-p differential spans via SENSE pin, enabling seamless integration with gain stages in medical and comms front-ends. |
| Low aperture jitter | 0.5 ps rms - preserves SNR at high input frequencies by minimizing sampling time uncertainty in undersampling applications. |
| Industrial temperature grade | Specified from –40°C to +85°C - validated for deployment in outdoor base stations, portable diagnostic equipment, and factory automation systems. |
Applications
| Ultrasound Beamforming | IF Sampling in Cellular Receivers |
|---|---|
Use Scenario: Digitizing echo return signals from phased-array transducers at 20–40 MSPS for real-time beam steering and image reconstruction. IC Role / Device Role / Timing Role: High-speed ADC capturing 12-bit samples with <70 dBc SNR to preserve tissue contrast resolution and Doppler velocity accuracy. Use Value: 500 MHz analog bandwidth enables direct sampling of 15–25 MHz ultrasound carriers without downconversion, reducing component count and phase mismatch errors. |
Use Scenario: Downconverting and digitizing CDMA-One or IS-95 IF signals centered at 45–70 MHz in base station receiver chains. IC Role / Device Role / Timing Role: IF-sampling ADC providing 40 MSPS throughput with 85 dBc SFDR to resolve adjacent-channel interference in multi-carrier environments. Use Value: Clock duty cycle stabilizer maintains timing integrity despite jittery local oscillator feeds, ensuring consistent EVM across temperature and voltage variations. |
| Battery-Powered Scopemeters | Low-Cost Digital Oscilloscopes |
Use Scenario: Portable handheld test equipment requiring sub-100 mW per channel power budget and >70 dBc SNR for waveform fidelity. IC Role / Device Role / Timing Role: Core digitizer delivering 12-bit resolution at 40 MSPS with integrated reference and low-noise SHA for compact front-end design. Use Value: 165 mW total power at 40 MSPS enables >4-hour battery life in dual-channel units using Li-ion cells, without active cooling. |
Use Scenario: Entry-level benchtop oscilloscopes targeting ≤$1,000 price point while maintaining ≥10 MHz analog bandwidth and 12-bit vertical resolution. IC Role / Device Role / Timing Role: Cost-optimized ADC with pin-compatible upgrade path from 10-bit predecessors (e.g., AD9214-65), easing legacy design migration. Use Value: TSSOP packaging and single-supply operation reduce PCB layer count and eliminate level-shifting components, cutting manufacturing cost by ~18% vs. LFCSP alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog-to-digital conversion applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9235BCPZ-40 | Same electrical specs but in 32-lead LFCSP package with lower θJA (32.5°C/W vs. 67.7°C/W); requires different PCB layout and reflow profile. | Better thermal performance for high-density, convection-cooled systems; not drop-in compatible with TSSOP footprints. | Select AD9235BCPZ-40 only when thermal headroom is constrained and board redesign is acceptable. |
| ADS5272IPFP | 12-bit, 40 MSPS, but uses serial LVDS output (not parallel CMOS); higher power (220 mW); no on-chip reference. | Suitable for space-constrained FPGAs with embedded SerDes; requires external reference and level-shifting, increasing system complexity. | Choose ADS5272IPFP only when board area is critical and FPGA interface supports LVDS serialization. |
Compared with AD9235BCPZ-40 and ADS5272IPFP, the AD9235BRUZ-40 offers optimal balance of ease of use (parallel CMOS outputs, integrated reference), thermal margin (TSSOP with exposed pad), and cost-effectiveness for mid-volume industrial and medical instrumentation designs.
Availability
AD9235BRUZ-40 is available at Aetrix Electronics and suitable for ultrasound equipment, IF sampling in communications receivers, and battery-powered instruments requiring stable component supply and long-term industrial-grade availability.
Supply support for AD9235BRUZ-40 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD9235 family was designed specifically for high-speed, low-power, precision digitization in communications infrastructure, medical imaging, and portable test equipment - emphasizing single-supply simplicity, on-chip integration, and industrial reliability.
FAQ
What is the maximum analog input frequency supported by the AD9235BRUZ-40?
The AD9235BRUZ-40 features a 500 MHz analog input bandwidth and maintains specified AC performance (e.g., 70.4 dBc SNR) for input frequencies up to 100 MHz. This enables undersampling applications such as direct IF digitization of 70 MHz cellular signals without external filtering or downconversion stages. The AD9235BRUZ-40 achieves this using a patented differential sample-and-hold amplifier optimized for wideband linearity.
Does the AD9235BRUZ-40 require an external voltage reference?
No, the AD9235BRUZ-40 integrates a precision voltage reference with selectable 1.0 V or 0.5 V output, configured via the SENSE pin. When enabled, it drives the internal reference network with ±5 mV accuracy (1 V mode) and supports 1 Vp-p or 2 Vp-p differential input spans. External references may be used, but are not required - simplifying bill-of-materials and layout for the AD9235BRUZ-40.
What is the purpose of the OTR pin on the AD9235BRUZ-40?
The OTR (Out-of-Range) pin on the AD9235BRUZ-40 is an active-high flag that asserts when the analog input exceeds the selected full-scale range (±FSR/2). It works in conjunction with the MSB to distinguish between low-side and high-side saturation events, enabling real-time clipping detection and adaptive gain control in ultrasound and spectrum analysis systems using the AD9235BRUZ-40.
Can the AD9235BRUZ-40 operate with a non-50% clock duty cycle?
Yes - the AD9235BRUZ-40 includes an integrated clock duty cycle stabilizer (DCS) that actively corrects input clock asymmetry. At 40 MSPS, it maintains full AC performance (SNR/SFDR) across a 30%–70% duty cycle range. This eliminates the need for external clock conditioning circuits and improves timing robustness in systems where the source clock originates from PLLs or microcontrollers with variable duty cycles driving the AD9235BRUZ-40.
What are the power supply requirements for the AD9235BRUZ-40?
The AD9235BRUZ-40 requires two independent supplies: AVDD (2.7 V–3.6 V) for analog circuitry and DRVDD (2.25 V–3.6 V) for digital outputs. Typical current draw is 55 mA on AVDD and 5 mA on DRVDD at 40 MSPS, totaling 165 mW. Both supplies must be decoupled locally - especially DRVDD, which requires a minimum 0.1 µF capacitor to DGND - to ensure stable operation of the AD9235BRUZ-40.
AD9235BRUZ-40 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 40M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.25V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9235BRUZ-40 FAQ
1.How can I place an order for AD9235BRUZ-40 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9235BRUZ-40 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9235BRUZ-40 reliable?
The price and inventory of AD9235BRUZ-40 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9235BRUZ-40 is usually 5 days.
3.What payment methods are accepted for AD9235BRUZ-40?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9235BRUZ-40 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9235BRUZ-40?
AD9235BRUZ-40 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9235BRUZ-40 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9235BRUZ-40?
For technical support, including AD9235BRUZ-40 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9235BRUZ-40 requirements.
6.How does Aetrix verify that AD9235BRUZ-40 is sourced from the original manufacturer or authorized distributors?
All AD9235BRUZ-40 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9235BRUZ-40 meets industry standards.
7.What is the process for return or replacement of AD9235BRUZ-40?
All AD9235BRUZ-40 units undergo pre-shipment inspection (PSI). If there is an issue with AD9235BRUZ-40, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9235BRUZ-40 part is unused and in its original packaging.
Return procedure for AD9235BRUZ-40:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD9235BRUZ-40 Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

