Analog Devices Inc. AD9236BRUZ-80
- Part No.:
- AD9236BRUZ-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AD9236BRUZ-80.pdf
- Description:
- IC ADC 12BIT PIPELINED 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,008
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Product details
Overview
AD9236BRUZ-80 from Analog Devices is a 12-bit, 80 MSPS analog-to-digital converter operating from a single 3 V supply (2.7 V to 3.6 V), featuring differential input with 500 MHz analog bandwidth, on-chip reference and sample-and-hold, and clock duty cycle stabilizer. It delivers SNR = 70.4 dBc and SFDR = 87.8 dBc at 40 MHz input, supporting IF sampling in communications receivers and high-end medical imaging systems.
For engineers reviewing the AD9236BRUZ-80 datasheet, AD9236BRUZ-80 pinout, AD9236BRUZ-80 application, or AD9236BRUZ-80 equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions for the 28-lead TSSOP package, confirmed alternatives with functional and application-level differences, and supply support for industrial and medical OEM deployments.
Technical Context
The AD9236BRUZ-80 employs a multistage differential pipelined architecture with output error correction logic to guarantee 12-bit accuracy and no missing codes across −40°C to +85°C. Its patented sample-and-hold amplifier supports both differential and single-ended configurations, with input bandwidth up to 100 MHz and flexible full-scale ranges of 1 Vp-p or 2 Vp-p.
It integrates a duty cycle stabilizer (DCS) that maintains performance over wide clock duty cycle variation, and features separate analog (AVDD) and digital output driver (DRVDD) supplies-enabling compatibility with 2.5 V and 3.3 V logic families. The OTR (out-of-range) signal provides overflow detection synchronized to the pipeline latency of 7 clock cycles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees monotonicity and no missing codes over full temperature range. |
| Sampling Rate | 80 MSPS - supports Nyquist-limited IF sampling up to 40 MHz with >70 dBc SNR. |
| SNR @ 40 MHz | 70.4 dBc - enables high-fidelity digitization of narrowband RF/IF signals in WCDMA/CDMA-2000. |
| SFDR @ 40 MHz | 87.8 dBc - suppresses spurious content critical for multi-carrier communication receiver front ends. |
| Power Consumption | 366 mW at 80 MSPS - achieves low power per sample (4.58 µW per conversion) for battery-powered instruments. |
| Analog Input Bandwidth | 500 MHz - allows direct sampling of wideband signals without external amplification or filtering. |
| Differential Nonlinearity | ±0.4 LSB - ensures accurate amplitude representation in medical ultrasound beamforming applications. |
| Pipeline Latency | 7 clock cycles - defines deterministic timing for real-time control loops and digital downconversion alignment. |
Pinout & Package
AD9236BRUZ-80 is packaged in a 28-lead TSSOP (RU-28) with exposed thermal pad not present; pinout is fully validated per Analog Devices Rev. C datasheet Figure 3 and Table 8.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OTR (Pin 1) | Out-of-Range Indicator | Active-high flag signaling ADC overflow; used with MSB to distinguish low/high saturation in real-time signal monitoring. |
| MODE (Pin 2) | Data Format & DCS Control | Selects offset binary/twos complement output and enables/disables duty cycle stabilizer for clock jitter tolerance. |
| SENSE (Pin 3) | Reference Mode Selection | Configures internal reference (1.0 V or 0.5 V) or enables external reference via VREF/REFT/REFB pins. |
| VIN+ / VIN– (Pins 9, 10) | Differential Analog Input | High-Z, 7 pF input capacitance; supports ac/dc coupling and common-mode voltage adjustment from 0.3 V to AVDD – 0.3 V. |
| CLK (Pin 13) | Single-Ended Clock Input | Accepts CMOS-level clock; DCS compensates for duty cycle as low as 30% or as high as 70% without SNR degradation. |
| D0–D11 (Pins 15–22, 25–28) | Parallel Digital Output Bus | 12-bit straight binary or twos complement data; outputs driven by DRVDD-supplied buffers (2.5 V or 3.3 V compatible). |
| PDWN (Pin 14) | Power-Down Control | Active-low input reducing power to 1.0 mW; wake-up time is 7 ms with standard 0.1 µF/10 µF decoupling on REFT/REFB. |
Key Features
| Feature | Design Value |
|---|---|
| Single 3 V supply with dual-rail output drivers | Eliminates need for separate 2.5 V/3.3 V logic supply; simplifies PCB power tree while maintaining interface flexibility. |
| On-chip voltage reference (1.0 V or 0.5 V) | Removes external reference IC and associated layout sensitivity; reduces BOM count and improves thermal stability. |
| Duty cycle stabilizer (DCS) | Enables use of non-50% clocks (e.g., PLL-derived or FPGA-generated) without SNR/SFDR penalty-critical for system-level clock sharing. |
| 7-cycle deterministic pipeline latency | Allows precise timing alignment in digital downconverters and real-time feedback control systems using fixed-latency compensation. |
| 500 MHz analog input bandwidth | Supports direct RF sampling up to L-band frequencies; avoids image-reject filter complexity in compact SDR front ends. |
| Industrial temperature range (−40°C to +85°C) | Validated operation in medical imaging enclosures and outdoor telecom base station environments without derating. |
Applications
| Medical Ultrasound Imaging | IF Sampling in Cellular Base Stations |
|---|---|
|
Use Scenario: Digitizing echo return signals from phased-array transducers at 40–50 MSPS for beamforming and Doppler processing. IC Role / Device Role / Timing Role: High-speed ADC capturing time-domain RF echoes with sub-1 ps aperture jitter to preserve phase coherence across channels. Use Value: 70.4 dBc SNR at 40 MHz enables detection of weak tissue boundaries; ±0.4 LSB DNL ensures accurate amplitude mapping for grayscale rendering. |
Use Scenario: Downconverting and digitizing 45 MHz IF signals from WCDMA/CDMA-2000 radio receivers in macrocell and small-cell base stations. IC Role / Device Role / Timing Role: IF-sampling ADC interfacing directly to quadrature demodulator outputs with differential input rejection of common-mode noise. Use Value: 87.8 dBc SFDR prevents adjacent-channel interference masking; 500 MHz input bandwidth accommodates wide IF filters without aliasing. |
| Battery-Powered Scopemeters | DTV Subsystem Digitizers |
|
Use Scenario: Portable handheld oscilloscopes requiring 80 MSPS sampling for 20 MHz analog bandwidth and real-time waveform capture. IC Role / Device Role / Timing Role: Low-power ADC core with 366 mW consumption and fast wake-up (7 ms) enabling responsive trigger-based acquisition. Use Value: Single 3 V supply eliminates level-shifting; OTR flag supports automatic vertical scale adjustment during overrange events. |
Use Scenario: Digitizing composite video or digital terrestrial TV IF signals (e.g., 36 MHz DVB-T carriers) in set-top box tuner modules. IC Role / Device Role / Timing Role: High-SFDR ADC rejecting harmonics from local oscillator leakage and mixer products in dense spectral environments. Use Value: Guaranteed no missing codes ensures accurate EVM measurement; 2 Vp-p input range matches typical IF amplifier output swing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9235BCPZ-80 | 12-bit, 80 MSPS, same pinout but in 32-lead LFCSP; lower θJA (32.5°C/W) and exposed paddle for improved thermal performance. | Better suited for thermally constrained PCB layouts (e.g., dense RF modules); requires rework for TSSOP footprint. | Select AD9235BCPZ-80 when thermal management is critical and LFCSP assembly capability exists. |
| AD9245BCPZ-80 | 14-bit, 80 MSPS, pin-compatible with AD9236BRUZ-80; higher resolution but increased power (500 mW) and larger die size. | Used where ENOB > 11.4 bits is required (e.g., high-dynamic-range radar digitizers); trades power and cost for precision. | Select AD9245BCPZ-80 only when 14-bit resolution is mandatory and system power budget permits +134 mW. |
Compared with AD9236BRUZ-80, AD9235BCPZ-80 offers superior thermal dissipation in space-constrained designs, while AD9245BCPZ-80 delivers 2 extra bits of resolution at the cost of higher power and no improvement in SFDR at 40 MHz-making AD9236BRUZ-80 optimal for balanced IF sampling where SNR/SFDR and power efficiency are prioritized.
Availability
AD9236BRUZ-80 is available at Aetrix Electronics and suitable for high-end medical imaging equipment, IF sampling in communications receivers, and battery-powered instruments requiring stable component supply across extended product lifecycles.
Supply support for AD9236BRUZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with R&D and manufacturing facilities worldwide.
The AD9236 product line was designed for high-speed, low-power digitization in communications, medical imaging, and test instrumentation-emphasizing SNR/SFDR integrity, thermal robustness, and system-level clock flexibility.
FAQ
What is the maximum analog input frequency supported by the AD9236BRUZ-80?
The AD9236BRUZ-80 has a specified analog input bandwidth of 500 MHz, and its sample-and-hold amplifier maintains excellent performance up to 100 MHz input frequency. At 100 MHz, SNR remains at 69.0 dBc and SFDR at 76.4 dBc per the Rev. C datasheet Table 2-validating use in undersampled IF architectures up to L-band frequencies.
Does the AD9236BRUZ-80 require an external reference voltage?
No, the AD9236BRUZ-80 includes an on-chip voltage reference configurable for 1.0 V or 0.5 V output via the SENSE pin. External reference is optional and enabled only when SENSE is grounded; otherwise, the internal reference drives VREF, REFT, and REFB pins-reducing external component count and layout sensitivity.
What is the purpose of the OTR pin on the AD9236BRUZ-80?
The OTR (Out-of-Range) pin on the AD9236BRUZ-80 is an active-high indicator that signals when the analog input exceeds the selected full-scale range. It operates synchronously with the 7-cycle pipeline latency and is used alongside the MSB to determine whether overflow is positive or negative-enabling real-time gain control and clipping detection in medical and communications systems.
Can the AD9236BRUZ-80 operate with a non-50% duty cycle clock?
Yes, the AD9236BRUZ-80 includes a dedicated clock duty cycle stabilizer (DCS) that compensates for wide variations in input clock duty cycle-from 30% to 70%-while maintaining full AC performance (SNR and SFDR). This feature is enabled via the MODE pin and eliminates the need for external clock conditioning circuits.
What is the power consumption of the AD9236BRUZ-80 in standby mode?
In standby mode, activated by pulling the PDWN pin high, the AD9236BRUZ-80 draws only 1.0 mW. Wake-up time is 7 ms under typical decoupling conditions (0.1 µF and 10 µF capacitors on REFT and REFB), making it suitable for power-gated systems like portable scopemeters and battery-backed data loggers.
AD9236BRUZ-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.25V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9236BRUZ-80 FAQ
1.How can I place an order for AD9236BRUZ-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9236BRUZ-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9236BRUZ-80 reliable?
The price and inventory of AD9236BRUZ-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9236BRUZ-80 is usually 5 days.
3.What payment methods are accepted for AD9236BRUZ-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9236BRUZ-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9236BRUZ-80?
AD9236BRUZ-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9236BRUZ-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9236BRUZ-80?
For technical support, including AD9236BRUZ-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9236BRUZ-80 requirements.
6.How does Aetrix verify that AD9236BRUZ-80 is sourced from the original manufacturer or authorized distributors?
All AD9236BRUZ-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9236BRUZ-80 meets industry standards.
7.What is the process for return or replacement of AD9236BRUZ-80?
All AD9236BRUZ-80 units undergo pre-shipment inspection (PSI). If there is an issue with AD9236BRUZ-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9236BRUZ-80 part is unused and in its original packaging.
Return procedure for AD9236BRUZ-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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