Analog Devices Inc. AD9262BCPZ-5
- Part No.:
- AD9262BCPZ-5
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad, CSP
- Datasheet:
-
AD9262BCPZ-5.pdf
- Description:
- IC ADC 16BIT SIGMA-DELTA 64LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD9262BCPZ-5 from Analog Devices is a dual-channel, 16-bit continuous-time sigma-delta analog-to-digital converter (ADC) optimized for quadrature baseband sampling in communications receivers. It delivers 85 dB SNR and −87 dBc SFDR up to 10 MHz input bandwidth, operates with 1.8 V analog supply and 1.8–3.3 V digital output supply, consumes 600 mW, and supports 5 MHz real/10 MHz complex input bandwidth. It is used in W-CDMA and LTE direct-conversion receiver front-ends.
For engineers reviewing the AD9262BCPZ-5 datasheet, AD9262BCPZ-5 pinout, AD9262BCPZ-5 application, or AD9262BCPZ-5 equivalent, key selection considerations include its 5 MHz analog input bandwidth specification, integrated dc/quadrature correction for I/Q channel matching, 64-lead LFCSP package thermal performance, and SPI-configurable decimation filter settings for flexible output data rate (30–160 MSPS).
Technical Context
The AD9262BCPZ-5 implements a 32× oversampled fifth-order continuous-time Σ-Δ modulator running at 640 MSPS, with integrated low-pass decimation filters and sample rate converters that reduce output data rate to user-selectable 30–160 MSPS. Its passive resistive input impedance (1 kΩ differential) eliminates need for external driver amplifiers in many applications.
It incorporates on-chip PLL clock multiplier for internal 640 MHz clock generation, integrated voltage reference (500 mV), and hardware-based dc and quadrature error estimation blocks that correct gain/phase mismatch between Channel A and Channel B-critical for complex signal processing in zero-IF architectures.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit - guarantees no missing codes over full industrial temperature range (−40°C to +85°C) |
| Analog Input Bandwidth | 5 MHz real / 10 MHz complex - defines usable signal spectrum without external antialiasing filters |
| SNR @ fIN = 1.2 MHz | 85.3 dB - determines dynamic range for narrowband cellular signals in W-CDMA/LTE bands |
| SFDR @ fIN = 1.2 MHz | −87 dBc - specifies spurious-free operation critical for multi-carrier GSM/EDGE interference rejection |
| Power Consumption | 600 mW - measured with PLL disabled, enabling thermal management in dense RF front-end layouts |
| Output Data Rate | 30–160 MSPS - programmable via decimation ratio, supporting flexible interface to FPGAs or DSPs |
| Noise Figure | 15 dB - referenced to 50 Ω source, enabling direct comparison with RF receiver chain NF budgets |
Pinout & Package
The AD9262BCPZ-5 is housed in a 64-lead LFCSP (Lead Frame Chip Scale Package) with exposed thermal pad (EPAD) soldered to analog ground for optimal thermal dissipation (θJC = 1.1°C/W). Package dimensions comply with CP-64-4 outline per Analog Devices documentation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK+, CLK− | Differential clock input | Accepts CMOS or LVPECL clocks; enables precise timing control of 640 MSPS modulator sampling |
| VIN+A, VIN−A / VIN+B, VIN−B | Differential analog inputs | 1 kΩ resistive input impedance simplifies anti-aliasing filter design and relaxes driver requirements |
| D0A–D15A, D0B–D15B | Parallel digital outputs | 16-bit dual-channel data bus; supports interleaved mode to reduce PCB routing complexity |
| DCO | Data clock output | Provides synchronous edge-aligned clock for reliable capture of parallel output data |
| ORA, ORB | Overrange indicators | Active-high flags signaling saturation on respective channels-enables real-time AGC feedback |
| SDIO, SCLK, CSB | SPI serial interface | Configures decimation ratio, data format (offset binary/Gray/twos complement), and power modes |
| RESET | Hardware reset | Asynchronous active-low input for deterministic initialization of internal state machines |
| AVDD, DVDD, DRVDD, CVDD | Supply rails | Separate analog (1.8 V), digital core (1.8 V), output driver (1.8–3.3 V), and clock (1.8 V) supplies enable noise isolation |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dc and quadrature correction | Automatically compensates for inter-channel gain/phase mismatch-eliminates manual calibration in I/Q receivers |
| On-chip PLL clock multiplier | Generates internal 640 MHz modulator clock from lower-frequency external reference-reduces system clock distribution complexity |
| Selectable bandwidth (5 MHz real) | Optimizes noise floor and alias rejection for specific RF band plans-avoids overdesigning front-end filtering |
| Resistive analog input (1 kΩ) | Enables direct connection to baluns or passive filters-removes need for high-speed op-amp drivers in many cases |
| Interleaved dual-channel output | Presents Channel A and B data on shared 16-bit bus-cuts PCB trace count by 50% versus separate buses |
Applications
| Baseband Quadrature Receiver | Quadrature Sampling Instrumentation |
|---|---|
Use Scenario: Direct-conversion RF front-end in LTE femtocell base station with dual-path I/Q sampling. IC Role / Device Role / Timing Role: Dual-channel ADC digitizing downconverted I/Q signals at 40 MSPS with integrated dc/quadrature correction. Use Value: 85.3 dB SNR and −87 dBc SFDR at 1.2 MHz enable accurate demodulation of 64-QAM LTE signals under adjacent channel interference. | Use Scenario: High-fidelity signal analyzer capturing wideband modulated waveforms for spectral compliance testing. IC Role / Device Role / Timing Role: Precision dual ADC providing synchronized I/Q samples for FFT-based real-time spectrum analysis. Use Value: 5 MHz analog bandwidth and 16-bit resolution support measurement of EVM and ACLR within ±0.3 dB accuracy across 2.1 GHz carrier. |
| Medical Ultrasound Beamforming | Radar Signal Acquisition |
Use Scenario: Digital beamformer in portable ultrasound system requiring low-power, high-SNR echo digitization. IC Role / Device Role / Timing Role: Dual-channel ADC sampling phased-array transducer outputs with matched channel latency. Use Value: 960-cycle fixed sample latency and <±0.035% offset error matching ensure coherent summation across 128 channels. | Use Scenario: Pulse-Doppler radar receiver digitizing IF signals from X-band mixer outputs. IC Role / Device Role / Timing Role: High-dynamic-range ADC capturing chirped radar returns with minimal harmonic distortion. Use Value: −92.8 dBc two-tone SFDR at 1.8/2.1 MHz enables detection of weak targets amid strong clutter reflections. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel sigma-delta ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9262BCPZ-10 | 10 MHz real / 20 MHz complex input bandwidth; higher SFDR at >4 MHz but lower SNR (82.8 dB @ 2.4 MHz) | Better suited for wideband radar or broadband instrumentation requiring >5 MHz instantaneous bandwidth | Select AD9262BCPZ-10 when input signal spectrum exceeds 5 MHz; AD9262BCPZ-5 offers superior SNR below 3 MHz |
| AD9643BCPZ-150 | Pipelined architecture; 14-bit, 150 MSPS; no integrated decimation or quadrature correction; requires external clock jitter cleanup | Targeted at high-speed time-domain acquisition where latency <100 ns is critical, not quadrature signal integrity | Choose AD9262BCPZ-5 for I/Q communication systems needing built-in correction; AD9643BCPZ-150 for oscilloscope-style sampling |
Compared with AD9262BCPZ-10 and AD9643BCPZ-150, the AD9262BCPZ-5 uniquely balances 5 MHz bandwidth, 85.3 dB SNR, and integrated I/Q correction-making it optimal for mid-band wireless infrastructure where power efficiency and channel matching outweigh raw speed.
Availability
AD9262BCPZ-5 is available at Aetrix Electronics and suitable for LTE femtocell development, medical ultrasound beamforming, and radar signal acquisition requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade (−40°C to +85°C).
Supply support for AD9262BCPZ-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, serving communications, industrial, automotive, and healthcare markets.
The AD9262 product line delivers continuous-time sigma-delta ADCs engineered for zero-IF and direct-conversion receiver architectures-emphasizing integrated signal conditioning, quadrature channel matching, and simplified RF front-end design.
FAQ
What is the analog input bandwidth specification for AD9262BCPZ-5?
The AD9262BCPZ-5 has a specified analog input bandwidth of 5 MHz (real) and 10 MHz (complex). This value is confirmed in Table 1 (DC Specifications) and Figure 10–15 of the Rev. A datasheet, where performance metrics are explicitly guaranteed over the full temperature range only for the AD9262BCPZ-5 variant. It defines the maximum frequency at which the device maintains specified SNR and SFDR performance without external filtering.
Does AD9262BCPZ-5 support interleaved dual-channel output mode?
Yes, the AD9262BCPZ-5 supports interleaved output mode, allowing Channel A and Channel B data to be multiplexed onto a single 16-bit bus. This capability is documented in the General Description section and functional block diagram (Figure 1), and reduces PCB routing complexity by halving the number of data traces required compared to independent parallel buses.
What power supply voltages does AD9262BCPZ-5 require?
The AD9262BCPZ-5 requires four independent supply rails: AVDD = 1.8 V (analog), DVDD = 1.8 V (digital core), DRVDD = 1.8 V to 3.3 V (output driver), and CVDD = 1.8 V (clock). These values are specified in Table 1 (DC Specifications) and Absolute Maximum Ratings (Table 6), with recommended operating ranges ensuring proper functionality across the industrial temperature range.
How does the integrated dc and quadrature correction work in AD9262BCPZ-5?
The AD9262BCPZ-5 incorporates dedicated hardware blocks that continuously estimate and correct dc offset and quadrature gain/phase mismatch between Channel A and Channel B. As described in the General Description and DC and Quadrature Error Correction section, this occurs in real time using internal calibration algorithms-no external processor or firmware intervention is needed, making it ideal for standalone I/Q receiver designs.
What is the typical SNR performance of AD9262BCPZ-5 at 1.2 MHz input frequency?
The AD9262BCPZ-5 achieves a typical SNR of 85.3 dB at fIN = 1.2 MHz, as measured with a −2 dBFS sine wave input, 40 MSPS output data rate, and PLL disabled (Table 2, AC Specifications). This value is guaranteed over the full industrial temperature range and reflects the device's optimized noise floor for mid-band cellular signal digitization.
AD9262BCPZ-5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 160M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- ADC
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 2
- Architecture:
- Sigma-Delta
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-LFCSP-VQ (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9262BCPZ-5 FAQ
1.How can I place an order for AD9262BCPZ-5 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9262BCPZ-5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9262BCPZ-5 reliable?
The price and inventory of AD9262BCPZ-5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9262BCPZ-5 is usually 5 days.
3.What payment methods are accepted for AD9262BCPZ-5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9262BCPZ-5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9262BCPZ-5?
AD9262BCPZ-5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9262BCPZ-5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9262BCPZ-5?
For technical support, including AD9262BCPZ-5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9262BCPZ-5 requirements.
6.How does Aetrix verify that AD9262BCPZ-5 is sourced from the original manufacturer or authorized distributors?
All AD9262BCPZ-5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9262BCPZ-5 meets industry standards.
7.What is the process for return or replacement of AD9262BCPZ-5?
All AD9262BCPZ-5 units undergo pre-shipment inspection (PSI). If there is an issue with AD9262BCPZ-5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9262BCPZ-5 part is unused and in its original packaging.
Return procedure for AD9262BCPZ-5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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