Analog Devices Inc. AD9267BCPZ
- Part No.:
- AD9267BCPZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Specialized ICs
- Package:
- 64-VFQFN Exposed Pad, CSP
- Datasheet:
-
AD9267BCPZ.pdf
- Description:
- IC SIGMA-DELTA MOD 64LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:4,237
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD9267BCPZ from Analog Devices is a dual-channel, 16-bit continuous-time sigma-delta modulator optimized for high-dynamic-range RF/IF digitization in wireless baseband receivers. It delivers 83 dB SNR and −88 dBc SFDR over 10 MHz real (20 MHz complex) bandwidth, operates at 640 MSPS with 4-bit LVDS output, and integrates on-chip PLL, voltage reference, and 1 kΩ resistive input impedance - enabling direct connection to passive front-ends in W-CDMA and LTE quadrature receivers.
For engineers reviewing the AD9267BCPZ datasheet, AD9267BCPZ pinout, AD9267BCPZ application, or AD9267BCPZ equivalent, key selection criteria include its 10 MHz analog input bandwidth, 15 dB noise figure, 1.8 V single-supply operation, 64-lead LFCSP package thermal performance, and dual-channel LVDS timing alignment via DCO± outputs.
Technical Context
The AD9267BCPZ employs a fifth-order continuous-time Σ-Δ architecture with 32× oversampling, where quantization noise shaping suppresses in-band noise while inherently rejecting aliases - eliminating external anti-alias filters. Its passive 1 kΩ differential input structure avoids active driver amplifiers and simplifies signal chain design.
Internal clock generation uses an integer-N PLL supporting 30–160 MHz reference inputs, or direct 608–672 MHz LVDS/CMOS/LVPECL clocking; digital outputs are 4-bit twos-complement LVDS at 640 MSPS with dedicated DCO± for latch synchronization and OR± flags per channel for overrange detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit effective resolution with guaranteed no missing codes - ensures monotonicity and full-scale linearity in precision IF sampling. |
| Analog Input Bandwidth | 10 MHz real (20 MHz complex) - supports wideband CDMA2000, W-CDMA, and LTE baseband signals without external filtering. |
| SNR / SFDR | 83 dB SNR and −88 dBc SFDR at 2.4–8.4 MHz input - enables high-fidelity demodulation of multi-carrier GSM/EDGE and 802.16x waveforms. |
| Noise Figure | 15 dB at −40 dBFS - relaxes linearity requirements of preceding LNA and mixer stages in receiver front-ends. |
| Power Consumption | 416 mW at 640 MSPS, PLL disabled - achieves high dynamic range with low power for thermally constrained industrial and telecom modules. |
| Digital Interface | 4-bit LVDS at 640 MSPS with DCO± and twos-complement format - provides deterministic timing for FPGA-based decimation and digital downconversion. |
| Supply Voltage | 1.8 V analog (AVDD), clock (CVDD), digital (DVDD), and driver (DRVDD) supplies - simplifies single-rail power design and reduces board-level complexity. |
Pinout & Package
The AD9267BCPZ is housed in a 64-lead LFCSP (CP-64-4) package with exposed thermal pad soldered to analog ground. Thermal resistance θJA is 22°C/W on a 4-layer board, requiring PCB-level thermal management for sustained 416 mW operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK+, CLK− | Differential clock input | Accepts CMOS/LVDS/LVPECL; determines 640 MSPS conversion rate - jitter < 1 ps rms preserves 83 dB SNR. |
| VIN+A/VIN−A, VIN+B/VIN−B | Dual differential analog inputs | 1 kΩ resistive termination; 2 V p-p full-scale swing - enables transformer- or amplifier-coupled IF interfaces without external biasing. |
| D0±A–D3±A, D0±B–D3±B | LVDS data outputs (4-bit per channel) | Twos-complement format at 640 MSPS; DCO± provides synchronous latch edge - eliminates setup/hold violations in FPGA capture logic. |
| OR+A/OR−A, OR+B/OR−B | Overrange indicators | Active-high differential flags per channel - enable real-time gain control or saturation monitoring in closed-loop receivers. |
| PLLMULT0–PLLMULT4, PLL_LOCKED | PLL configuration and status | 5-pin mode selection sets integer-N ratio; PLL_LOCKED asserts when internal 640 MHz clock is stable - critical for system boot sequencing. |
| VREF, CFILT | Reference and filter terminals | Internal 0.5 V reference with 10 µF decoupling on CFILT - stabilizes bias current for input resistors and DAC feedback network. |
Key Features
| Feature | Design Value |
|---|---|
| Continuous-time Σ-Δ architecture | 5th-order loop filter with 32× oversampling - provides inherent alias rejection, removing need for external anti-alias filters in IF sampling. |
| Passive 1 kΩ differential input | Eliminates requirement for high-linearity driver amplifiers - reduces component count, power, and distortion in wideband receiver signal chains. |
| On-chip PLL clock multiplier | Accepts 30–160 MHz reference clock and generates internal 640 MHz sampling clock - avoids high-frequency clock distribution challenges. |
| Integrated 0.5 V voltage reference | Unbuffered internal reference with 10 kΩ series impedance - requires 10 µF decoupling on VREF and CFILT to maintain 15 dB noise figure. |
| Dual-channel LVDS interface with DCO± | 4-bit data + dedicated differential data clock per channel - ensures timing margin for FPGA-based digital signal processing at 640 MSPS. |
Applications
| Baseband Quadrature Receiver | RF Instrumentation |
|---|---|
Use Scenario: Digitizing I/Q IF signals from zero-IF or low-IF mixers in LTE femtocell base stations. IC Role / Device Role / Timing Role: Dual-channel Σ-Δ modulator performing high-fidelity, wideband analog-to-digital conversion with synchronized sampling clocks. Use Value: 10 MHz real bandwidth and 83 dB SNR support simultaneous multi-carrier reception without AGC complexity or external filtering. |
Use Scenario: High-accuracy spectral analysis of modulated RF signals in vector signal analyzers. IC Role / Device Role / Timing Role: Precision IF sampling front-end delivering low-noise, high-SFDR digitization for FFT-based signal characterization. Use Value: −88 dBc SFDR and 15 dB noise figure enable clean measurement of adjacent-channel leakage and harmonic distortion in 5G test equipment. |
| Software-Defined Radio (SDR) | Defense Radar IF Processing |
Use Scenario: Reconfigurable wideband receiver in military SDR platforms operating across multiple waveform standards. IC Role / Device Role / Timing Role: Dual ADC core providing flexible, high-dynamic-range digitization with programmable PLL and SPI configuration. Use Value: Serial SPI interface and PLL_MULT pins allow runtime reconfiguration of sampling clock for adaptive waveform support. |
Use Scenario: Pulse-Doppler radar IF digitization requiring high spurious-free dynamic range and temperature stability. IC Role / Device Role / Timing Role: Dual-channel modulator capturing chirped IF returns with minimal in-band noise and aliasing artifacts. Use Value: Industrial temperature range (−40°C to +85°C) and <−120 dBc two-tone SFDR ensure reliable target detection in harsh environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel sigma-delta modulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9268BCPZ-125 | 125 MSPS, 16-bit, dual-channel pipelined ADC - lower speed, higher power (750 mW), no integrated PLL or Σ-Δ noise shaping. | Suitable for lower-bandwidth IF sampling where SNR > 78 dB suffices and external clocking is preferred. | Select AD9268BCPZ-125 only if system clocking infrastructure already supports 125 MHz and anti-alias filtering is acceptable. |
| ADS58C20IRGCT | 200 MSPS, 11-bit, dual-channel pipeline ADC - higher speed than AD9267BCPZ's effective Nyquist but lower resolution and no continuous-time architecture. | Used in broadband cable modem receivers where 11-bit ENOB and 200 MSPS meet DOCSIS 3.1 requirements. | Choose ADS58C20IRGCT when cost-sensitive designs prioritize sample rate over dynamic range and can accommodate external filtering. |
Compared with AD9267BCPZ, AD9268BCPZ-125 trades oversampling and alias rejection for simpler interface and lower cost at reduced bandwidth, while ADS58C20IRGCT offers higher throughput but sacrifices 5+ bits of effective resolution and inherent anti-aliasing - making AD9267BCPZ uniquely suited for wideband, filterless IF digitization.
Availability
AD9267BCPZ is available at Aetrix Electronics and suitable for baseband quadrature receivers, RF instrumentation, software-defined radio, and defense radar IF processing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AD9267BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, automotive, and aerospace markets since 1965.
The AD9267BCPZ belongs to Analog Devices' high-speed continuous-time sigma-delta modulator product line, designed specifically for wideband, low-noise IF digitization in next-generation wireless infrastructure and test equipment.
FAQ
What is the maximum analog input frequency supported by the AD9267BCPZ?
The AD9267BCPZ supports a 10 MHz real (20 MHz complex) analog input bandwidth, verified per AC specifications in the datasheet. At 2.4–8.4 MHz input frequencies, it maintains 83 dB SNR and −88 dBc SFDR - confirming full performance within this band. Operation beyond 10 MHz results in roll-off due to internal loop filter response, not aliasing, as the continuous-time architecture inherently suppresses out-of-band energy.
Does the AD9267BCPZ require an external anti-alias filter?
No, the AD9267BCPZ does not require an external anti-alias filter. Its fifth-order continuous-time Σ-Δ architecture provides inherent alias rejection through noise shaping - the quantization noise transfer function places zeros in all alias bands, suppressing aliased components without passive or active filtering. This is confirmed in the Theory of Operation and Analog Input Considerations sections of the AD9267BCPZ datasheet.
How is the AD9267BCPZ clocked - via internal PLL or external source?
The AD9267BCPZ supports both clocking modes: an on-chip integer-N PLL accepts 30–160 MHz reference inputs and generates the internal 640 MHz sampling clock, or it can be directly clocked with 608–672 MHz LVDS/CMOS/LVPECL signals. The PLL_LOCKED pin indicates lock status, and PLLMULT0–PLLMULT4 pins configure the multiplication ratio - enabling flexible clock tree design in systems like LTE base stations.
What is the purpose of the OR± pins on the AD9267BCPZ?
The OR+A/OR−A and OR+B/OR−B pins on the AD9267BCPZ are differential overrange indicators that assert when input signal amplitude exceeds full-scale (±1 V differential). They provide real-time saturation detection per channel - used in automatic gain control (AGC) loops or FPGA-based monitoring to prevent clipping in wide dynamic range applications such as multicarrier GSM/EDGE receivers.
Can the AD9267BCPZ operate with an external voltage reference?
Yes, the AD9267BCPZ supports external reference operation. Setting Serial Register 0x18[6] disables the internal 0.5 V unbuffered reference, allowing connection of a precision external source like the ADR130B. The internal reference must be decoupled with 10 µF on VREF and CFILT; external references require matching impedance and low-noise layout to preserve the specified 15 dB noise figure and 83 dB SNR performance.
AD9267BCPZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sigma-Delta Modulator
- Applications:
- Wireless Communication Systems
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-LFCSP-VQ (9x9)
- Grade:
- -
- Qualification:
- -
AD9267BCPZ FAQ
1.How can I place an order for AD9267BCPZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9267BCPZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9267BCPZ reliable?
The price and inventory of AD9267BCPZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9267BCPZ is usually 5 days.
3.What payment methods are accepted for AD9267BCPZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9267BCPZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9267BCPZ?
AD9267BCPZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9267BCPZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9267BCPZ?
For technical support, including AD9267BCPZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9267BCPZ requirements.
6.How does Aetrix verify that AD9267BCPZ is sourced from the original manufacturer or authorized distributors?
All AD9267BCPZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9267BCPZ meets industry standards.
7.What is the process for return or replacement of AD9267BCPZ?
All AD9267BCPZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9267BCPZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9267BCPZ part is unused and in its original packaging.
Return procedure for AD9267BCPZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD9267BCPZ Tags

-
CAP200DG-TL
Power Integrations

-
ATSHA204A-MAHDA-T
Microchip Technology

-
ATSHA204A-SSHDA-T
Microchip Technology

-
ATSHA204A-STUCZ-T
Microchip Technology
-
ATECC608B-MAHDA-T
Microchip Technology
-
ATECC608B-MAHCZ-S
Microchip Technology

-
ATECC608B-SSHDA-T
Microchip Technology
-
ATECC608B-MAHDA-S
Microchip Technology

-
ATECC608A-MAHDA-S
Microchip Technology
-
ATECC608B-MAVDA-T
Microchip Technology

-
ATECC608A-SSHDA-T
Microchip Technology

-
ATECC508A-MAHDA-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

