My Inquiry
My Account
Analog Devices Inc. AD9268BCPZ-105
- Part No.:
- AD9268BCPZ-105
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad, CSP
- Datasheet:
-
AD9268BCPZ-105.pdf
- Description:
- IC ADC 16BIT PIPELINED 64LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,262
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD9268BCPZ-105 from Analog Devices is a dual, 16-bit, 105 MSPS analog-to-digital converter (ADC) designed for high-performance IF sampling in communications infrastructure. It features differential 650 MHz analog input bandwidth, 78.2 dBFS SNR at 70 MHz input, 88 dBc SFDR, and operates from a single 1.8 V analog supply with separate 1.8 V CMOS or LVDS digital output drivers. It is used in multimode 3G/4G receivers and I/Q demodulation systems requiring precise dual-channel digitization.
For engineers reviewing the AD9268BCPZ-105 datasheet, AD9268BCPZ-105 pinout, AD9268BCPZ-105 application, or AD9268BCPZ-105 equivalent, key selection considerations include its 105 MSPS sample rate, dual-channel 16-bit resolution, on-chip dither for SFDR enhancement, integer clock divider (1–8), and support for both CMOS and LVDS output interfaces in a 64-lead LFCSP package.
Technical Context
The AD9268BCPZ-105 implements a multistage differential pipelined ADC architecture with integrated error correction logic per channel. Its analog front end includes wideband differential sample-and-hold amplifiers and supports flexible input ranges (1–2 Vp-p) with programmable internal voltage reference and optional on-chip dither.
Digital interface flexibility is provided via a 3-wire SPI for configuration of data formatting (offset binary/twos complement/gray), clock duty cycle stabilization (DCS), power-down modes, and BIST. Channel synchronization is supported through dedicated SYNC and multichip sync capability, while latency is fixed at 12 cycles (CMOS) or 12/12.5 cycles (LVDS).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit - Enables high dynamic range digitization of narrowband and wideband RF signals without quantization noise limiting system sensitivity. |
| Sample Rate | 105 MSPS - Supports Nyquist-sampled IF inputs up to ~52.5 MHz or undersampled RF carriers up to 300 MHz using bandpass sampling. |
| SNR @ 70 MHz | 78.2 dBFS - Delivers >12.6 ENOB at 70 MHz input, critical for maintaining EVM in LTE/W-CDMA baseband processing. |
| SFDR @ 70 MHz | 88 dBc - Ensures strong interferer rejection in dense spectral environments such as multicarrier cellular base stations. |
| Analog Input BW | 650 MHz - Allows direct sampling of first IF stages (e.g., 180–220 MHz) without external filtering degradation. |
| Power @ 105 MSPS | 590 mW (CMOS) / 685 mW (LVDS) - Balances performance and thermal load in compact, air-cooled wireless equipment. |
| Supply Voltages | AVDD = 1.8 V, DRVDD = 1.8 V - Simplifies power delivery with single low-voltage rail for analog core and configurable digital I/O. |
Pinout & Package
The AD9268BCPZ-105 is housed in a 64-lead, 9 mm × 9 mm LFCSP package with exposed thermal pad (AGND) requiring solder connection to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK+, CLK− | Differential clock input | Accepts CMOS/LVDS/LVPECL clocks; internal bias enables robust timing acquisition with <0.07 ps rms jitter aperture uncertainty. |
| VIN+A, VIN−A / VIN+B, VIN−B | Differential analog inputs (Ch A/B) | 650 MHz bandwidth, 200 Ω input impedance; supports 1–2 Vp-p swing and DC-coupled or AC-coupled signal paths. |
| D0A–D15A, D0B–D15B | Parallel digital outputs | 16-bit CMOS or LVDS outputs per channel; LVDS mode provides ANSI-compliant 290–400 mV differential swing for noise immunity. |
| DCOA, DCOB | Data clock outputs | Source-synchronous LVDS/CMOS clocks aligned to respective channel data; enables deterministic timing capture in FPGA receivers. |
| SYNC | Channel synchronization input | Enables deterministic phase alignment across multiple AD9268 devices in time-interleaved or MIMO configurations. |
| CSB, SCLK/DFS, SDIO/DCS | SPI serial interface | 3-wire interface for configuring data format, DCS enable, power modes, and BIST-no external pull-ups required for CSB. |
| PDWN, OEB | Power and output control | Asynchronous power-down (<2.5 mW) and output enable allow rapid channel gating during TDD burst intervals. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip dither | Improves SFDR by ≥10 dB at low-input levels (e.g., −23 dBFS), enabling clean digitization of weak adjacent channels without external noise injection. |
| Duty cycle stabilizer (DCS) | Compensates for clock duty cycle distortion, maintaining SNR/SFDR performance even with 40%–60% input clock duty cycle variation. |
| Programmable voltage reference | Internal 1.0 V reference with ±12 mV error; eliminates need for external precision reference and reduces BOM count in space-constrained designs. |
| Built-in self-test (BIST) | User-configurable digital pattern generation (ramp, checkerboard, pseudo-random) allows in-system ADC functional verification without analog stimulus. |
| Integer clock divider (1–8) | Allows use of higher-frequency, lower-jitter master clocks (e.g., 840 MHz ÷ 8 = 105 MSPS), improving phase noise margin in RF sampling architectures. |
Applications
| Cellular Base Station Receiver | MIMO Radio Front End |
|---|---|
|
Use Scenario: Digitizing dual IF outputs from quadrature downconverters in macrocell BTS supporting LTE FDD/TDD and 5G NR. IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC providing synchronized I/Q data streams to FPGA-based digital downconverters. Use Value: 95 dB crosstalk and matched gain/offset ensure accurate channel calibration and beamforming weight computation. |
Use Scenario: Capturing spatially diverse antenna signals in 4×4 or 8×8 MIMO transceivers for real-time channel estimation. IC Role / Device Role / Timing Role: Synchronized dual ADC capturing parallel RF paths with sub-100 ps inter-channel skew via SYNC and multichip sync. Use Value: Fixed 12-cycle latency and deterministic pipeline delay enable coherent time-aligned processing across all receive chains. |
| Software-Defined Radio (SDR) | Ultrasound Beamformer |
|
Use Scenario: Wideband digitization in reconfigurable military/commercial SDR platforms covering 10 MHz–300 MHz spectrum. IC Role / Device Role / Timing Role: High-SFDR ADC enabling simultaneous reception of multiple independent waveforms (e.g., GPS + comms + radar). Use Value: 88 dBc SFDR at 70 MHz and 80 dBc at 200 MHz ensures minimal spurious mixing in multi-band concurrent operation. |
Use Scenario: Sampling echo return signals from phased-array ultrasound transducers operating at 5–15 MHz center frequencies. IC Role / Device Role / Timing Role: Low-noise dual ADC converting analog beamformed RF echoes with <2.27 LSBrms input-referred noise. Use Value: −153.6 dBm/Hz noise floor preserves weak deep-tissue signal integrity for improved image contrast resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 16-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9268BCPZ-125 | Higher sample rate (125 MSPS); 77.2 dBFS SNR @ 70 MHz; 777 mW power at 125 MSPS. | Required when IF bandwidth exceeds 62.5 MHz or undersampling up to 300 MHz demands tighter Nyquist margin. | Select AD9268BCPZ-125 only if system clocking and thermal design accommodate +16% power and +19% sample rate overhead. |
| AD9258BCPZ-105 | 14-bit resolution; 73.5 dBFS SNR @ 70 MHz; pin-compatible but lacks on-chip dither and has lower SFDR (83 dBc). | Suitable for cost-sensitive, lower-dynamic-range applications where 16-bit ENOB is not required (e.g., narrowband IoT gateways). | Choose AD9258BCPZ-105 for reduced BOM cost and power (450 mW) when 12-bit ENOB suffices and SFDR >85 dBc is not mandatory. |
Compared with AD9268BCPZ-125, the AD9268BCPZ-105 trades 20 MSPS sample rate and ~1 dB SNR for 185 mW lower power and relaxed clock distribution; versus AD9258BCPZ-105, it delivers +2 bits resolution and +5 dB SFDR at identical pinout and footprint-enabling seamless upgrade path in existing layouts.
Availability
AD9268BCPZ-105 is available at Aetrix Electronics and suitable for cellular infrastructure, MIMO radio front ends, and ultrasound beamformer designs requiring stable component supply, long-term obsolescence management, and traceable sourcing.
Supply support for AD9268BCPZ-105 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD9268 belongs to Analog Devices' high-speed ADC product line, engineered for demanding communications and instrumentation applications where resolution, speed, and spectral purity must coexist within tight power and size constraints.
FAQ
What is the maximum analog input frequency supported by the AD9268BCPZ-105?
The AD9268BCPZ-105 supports analog input frequencies up to 300 MHz using IF sampling techniques. Its 650 MHz analog input bandwidth ensures minimal amplitude and phase roll-off at these frequencies, and its 105 MSPS sample rate enables bandpass sampling of signals centered well above the Nyquist frequency-critical for direct RF sampling in modern wireless receivers. The AD9268BCPZ-105 maintains 77.2 dBFS SNR even at 70 MHz input, confirming usable performance across its full small-signal bandwidth.
Does the AD9268BCPZ-105 support both CMOS and LVDS digital outputs simultaneously?
No-the AD9268BCPZ-105 supports either CMOS or LVDS output mode, selected at power-up via the SENSE pin configuration. In CMOS mode, outputs drive 1.8 V logic levels with 1.75 V high-level voltage at 0.5 mA load; in LVDS mode, they deliver ANSI-compliant differential swings (290–400 mV) with 1.15–1.35 V common-mode offset. The AD9268BCPZ-105 does not support concurrent CMOS+LVDS operation, and mode selection is static-not runtime reconfigurable.
How does the on-chip dither function improve SFDR in the AD9268BCPZ-105?
The AD9268BCPZ-105's on-chip dither injects controlled broadband noise into the ADC transfer function, randomizing quantization error harmonics and converting them into lower-level wideband noise. At −23 dBFS input, dither improves SFDR by ≥10 dB (e.g., from 89 dBFS to 106 dBFS at 70 MHz), directly enhancing adjacent-channel rejection in multicarrier systems. This eliminates the need for external dither circuits and preserves board space while maintaining the AD9268BCPZ-105's 750 mW total power envelope.
What is the purpose of the SYNC pin on the AD9268BCPZ-105?
The SYNC pin on the AD9268BCPZ-105 provides deterministic alignment of sampling instants across multiple devices in multichip configurations. When asserted synchronously with the ADC clock, it resets internal pipeline stages to ensure phase-coherent sampling across channels-essential for MIMO beamforming, time-interleaved ADC arrays, and calibrated I/Q receiver pairs. The AD9268BCPZ-105 guarantees <100 ps inter-device skew when SYNC is used with matched trace lengths and proper termination.
Can the AD9268BCPZ-105 operate with a single 1.8 V supply for both analog and digital sections?
No-the AD9268BCPZ-105 requires two independent 1.8 V supplies: AVDD for the analog core (including sample-and-hold and reference circuitry) and DRVDD for the digital output drivers. While both rails are nominally 1.8 V, they must be separately decoupled and routed to avoid coupling digital switching noise into the sensitive analog path. The AD9268BCPZ-105 specifies distinct current draws (390 mA AVDD, 89 mA DRVDD in LVDS mode), confirming the need for independent regulation and filtering.
AD9268BCPZ-105 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 105M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-LFCSP-VQ (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9268BCPZ-105 FAQ
1.How can I place an order for AD9268BCPZ-105 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9268BCPZ-105 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9268BCPZ-105 reliable?
The price and inventory of AD9268BCPZ-105 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9268BCPZ-105 is usually 5 days.
3.What payment methods are accepted for AD9268BCPZ-105?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9268BCPZ-105 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9268BCPZ-105?
AD9268BCPZ-105 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9268BCPZ-105 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9268BCPZ-105?
For technical support, including AD9268BCPZ-105 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9268BCPZ-105 requirements.
6.How does Aetrix verify that AD9268BCPZ-105 is sourced from the original manufacturer or authorized distributors?
All AD9268BCPZ-105 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9268BCPZ-105 meets industry standards.
7.What is the process for return or replacement of AD9268BCPZ-105?
All AD9268BCPZ-105 units undergo pre-shipment inspection (PSI). If there is an issue with AD9268BCPZ-105, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9268BCPZ-105 part is unused and in its original packaging.
Return procedure for AD9268BCPZ-105:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD9268BCPZ-105 Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
