My Inquiry
My Account
Analog Devices Inc. AD9460-105LVDSPCBZ
- Part No.:
- AD9460-105LVDSPCBZ
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
AD9460-105LVDSPCBZ.pdf
- Description:
- BOARD EVALUATION AD9460-105
- Quantity:
- Payment:
- Shipping:
Inventory:3,598
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AD9460-105LVDSPCBZ from Analog Devices is a 16-bit, 105 MSPS analog-to-digital converter (ADC) with on-chip track-and-hold, LVDS/CMOS outputs, and internal reference. It delivers 77.2 dBFS SNR and 84 dBc SFDR at 170 MHz input (3.4 Vp-p, 105 MSPS), supporting high-fidelity digitization in radar IF receivers and MRI baseband acquisition.
For engineers reviewing the AD9460-105LVDSPCBZ datasheet, AD9460-105LVDSPCBZ pinout, AD9460-105LVDSPCBZ application, or AD9460-105LVDSPCBZ equivalent, this evaluation board enables rapid validation of 105 MSPS sampling performance, differential analog input interface, LVDS timing capture, and SFDR-optimized front-end configuration under industrial temperature conditions.
Technical Context
The AD9460-105LVDSPCBZ implements a 16-bit pipeline ADC architecture with integrated clock duty cycle stabilizer (DCS), adjustable full-scale input range (2.0–4.0 Vp-p), and selectable output data format (offset binary or twos complement). Its analog input stage features buffered differential inputs with 615 MHz bandwidth and programmable common-mode voltage (3.2–3.9 V).
Digital interface options include ANSI-644-compliant LVDS outputs (16-bit parallel + DCO ±) or CMOS outputs, both supported by dedicated DRVDD (3.3 V) and DRGND. The SFDR control pin allows analog front-end optimization for <200 MHz or >200 MHz input frequencies, directly affecting AVDD2 power consumption.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Sampling Rate | 105 MSPS guaranteed maximum rate - enables Nyquist-limited digitization of signals up to 52.5 MHz without aliasing. |
| Resolution | 16-bit linear resolution - provides 65,536 distinct digital codes with ±0.5 LSB typical DNL and ±3.0 LSB typical INL. |
| SNR / SFDR | 77.2 dBFS SNR / 84 dBc SFDR @ 170 MHz input - supports high-dynamic-range signal capture in multicarrier cellular and radar applications. |
| Analog Input | 3.4 Vp-p differential full-scale range (internal 1.7 V reference) - matches standard RF transformer outputs and simplifies driver design. |
| Output Interface | LVDS-compatible (ANSI-644) 16-bit parallel data + DCO± - reduces EMI and enables reliable high-speed capture over PCB traces up to 15 cm. |
| Jitter Performance | 60 fsrms aperture uncertainty - preserves ENOB >12.4 bits at 170 MHz input frequency. |
| Power Supply | 3.3 V (AVDD1, DRVDD) and 5.0 V (AVDD2) supplies - separates analog and digital domains to minimize noise coupling. |
| Operating Range | −40°C to +85°C industrial temperature range - validated for embedded medical and defense systems requiring thermal robustness. |
Pinout & Package
AD9460-105LVDSPCBZ is an evaluation board for the AD9460BSVZ-105 IC, which uses a Pb-free, 100-lead TQFP_EP package with exposed heat sink soldered to AGND. The board routes all 100 pins to accessible test points and connectors per the AD9460's LVDS mode pin configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+, VIN− | Differential analog input | Accepts 3.4 Vp-p buffered input; common-mode voltage set to 3.5 V internally or externally via SENSE pin. |
| CLK+, CLK− | Differential sampling clock input | Accepts low-voltage differential clock; DCS MODE pin enables duty cycle correction to maintain timing accuracy. |
| D0+ to D15+, D0− to D15− | LVD S data outputs (16-bit) | ANSI-644-compliant LVDS pairs; each bit pair drives 100 Ω termination; supports 105 MSPS sustained data rate. |
| DCO+, DCO− | Data clock output | Synchronous LVDS clock aligned to data edges; used for timing-critical FPGA or ASIC capture with minimal skew. |
| OR+, OR− | Out-of-range indicator | Differential flag signaling analog input saturation; enables real-time clipping detection without host processor overhead. |
| SFDR | Front-end optimization control | Connect to AGND for <200 MHz inputs (optimal SFDR); connect to AVDD1 for >200 MHz inputs (increases AVDD2 current ~20 mW). |
Key Features
| Feature | Design Value |
|---|---|
| On-chip track-and-hold with buffered inputs | Eliminates need for external THA or high-bandwidth op-amp drivers; supports 615 MHz analog input bandwidth. |
| Internal 1.7 V reference with SENSE pin control | Enables 3.4 Vp-p full-scale operation without external reference IC; SENSE = AGND selects internal mode. |
| Configurable LVDS/CMOS output mode | OUTPUT MODE pin selects interface type; LVDS reduces switching noise and improves signal integrity at 105 MSPS. |
| Clock duty cycle stabilizer (DCS) | Compensates for clock asymmetry; maintains aperture jitter ≤60 fsrms across wide duty cycle variation (40–60%). |
| Out-of-range (OR) monitoring outputs | Differential OR+ / OR− signals provide immediate saturation alert, enabling adaptive gain control or fault logging. |
| 100-lead TQFP_EP with exposed heat sink | Thermal resistance θJA = 19.8°C/W (heat sink soldered); requires direct connection of exposed pad to AGND plane for thermal compliance. |
Applications
| MRI Baseband Digitization | Radar IF Receiver |
|---|---|
Use Scenario: Digitizing low-noise, wide-dynamic-range analog outputs from MRI gradient and RF receive coils operating at baseband (DC–20 MHz). IC Role / Device Role / Timing Role: High-linearity ADC capturing 16-bit samples at 105 MSPS to preserve SNR >77 dBFS for image reconstruction fidelity. Use Value: Internal reference and buffered inputs eliminate external components; LVDS outputs reduce noise coupling into sensitive analog front-end. |
Use Scenario: Sampling intermediate frequency (IF) signals from radar downconverters at 70–170 MHz with minimal distortion. IC Role / Device Role / Timing Role: Pipeline ADC providing 84 dBc SFDR at 170 MHz input, enabling accurate pulse-Doppler processing. Use Value: SFDR pin allows front-end tuning for optimal spurious performance; DCS maintains timing accuracy despite imperfect clock sources. |
| Communications Instrumentation | Multicarrier Cellular Receiver |
Use Scenario: Capturing broadband test waveforms in vector signal analyzers and protocol testers requiring >100 MSPS sampling. IC Role / Device Role / Timing Role: High-speed ADC with 60 fsrms jitter enabling ENOB >12.4 bits at 225 MHz input for modulation accuracy validation. Use Value: Two-tone SFDR of 90 dBFS at 139/140 MHz validates adjacent-channel interference rejection in LTE/NR testing. |
Use Scenario: Simultaneous digitization of multiple carrier bands in base station receivers using wideband IF sampling. IC Role / Device Role / Timing Role: 16-bit ADC supporting 105 MSPS to resolve 20+ carriers within 100 MHz instantaneous bandwidth. Use Value: Programmable input range (2.0–4.0 Vp-p) accommodates varying signal levels across carrier aggregation scenarios. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9461-105EBZ | Same AD9460 silicon, but configured for CMOS output mode and different layout; lacks LVDS termination network and DCO routing. | Preferred for FPGA interfaces with CMOS I/O banks and short trace lengths (<5 cm); higher power draw than LVDS mode. | Select AD9461-105EBZ only when LVDS infrastructure is unavailable and system-level EMI constraints permit CMOS switching noise. |
| ADS5463EVM | Texas Instruments 13-bit, 500 MSPS ADC with JESD204B serial interface; no LVDS parallel outputs or internal reference. | Targets ultra-wideband applications (>200 MHz IF) where serialization reduces pin count; requires external clock conditioner and reference. | Choose ADS5463EVM for >250 MSPS throughput needs or space-constrained designs; not drop-in compatible due to interface, resolution, and supply differences. |
Compared with AD9460-105LVDSPCBZ, AD9461-105EBZ trades LVDS noise immunity for simpler interfacing, while ADS5463EVM sacrifices resolution and ease-of-use for raw speed and serial scalability-neither offers pin or functional equivalence.
Availability
AD9460-105LVDSPCBZ is available at Aetrix Electronics and suitable for MRI receiver development, radar IF digitization, communications instrumentation, and multicarrier cellular receiver prototyping requiring stable component supply and full evaluation support.
Supply support for AD9460-105LVDSPCBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and DSP technologies, serving precision instrumentation, communications, and industrial markets since 1965.
The AD9460 product line delivers high-resolution, high-speed ADCs optimized for demanding IF/baseband digitization in medical imaging, radar, and test equipment-prioritizing SNR, SFDR, and ease of integration over raw speed alone.
FAQ
What is the primary function of the AD9460-105LVDSPCBZ evaluation board?
The AD9460-105LVDSPCBZ is a fully assembled and tested evaluation platform for the AD9460BSVZ-105 16-bit, 105 MSPS ADC. It provides standardized SMA connectors for analog input, clock, and LVDS data, onboard power regulation, and documented layout practices to validate timing margins, SNR, and SFDR performance before custom PCB design.
Does the AD9460-105LVDSPCBZ support both LVDS and CMOS output modes?
No-the AD9460-105LVDSPCBZ is specifically configured for LVDS operation, with matched 100 Ω terminations on all D0–D15 and DCO differential pairs. To evaluate CMOS mode, users must refer to the AD9461-105EBZ board or modify the AD9460-105LVDSPCBZ per the AD9460 datasheet's CMOS pinout and termination guidelines.
How is the SFDR pin used on the AD9460-105LVDSPCBZ?
On the AD9460-105LVDSPCBZ, the SFDR pin is routed to a header for user configuration. Connecting it to AGND optimizes spurious-free dynamic range for analog inputs below 200 MHz; connecting it to AVDD1 improves SFDR above 200 MHz at the cost of ~20 mW increased AVDD2 current-verified in AD9460-105 characterization data.
What power supplies are required to operate the AD9460-105LVDSPCBZ?
The AD9460-105LVDSPCBZ requires three regulated supplies: +3.3 V for AVDD1 and DRVDD, +5.0 V for AVDD2, and isolated analog/digital grounds. The board includes on-board LDOs and filtering; input is typically a single +5 V or +12 V source fed to the barrel jack or screw terminals per the user guide.
Can the AD9460-105LVDSPCBZ be used for production systems?
No-the AD9460-105LVDSPCBZ is an evaluation board intended for lab validation and prototype development only. It is not qualified for continuous operation in production environments. For volume deployment, designers must integrate the AD9460BSVZ-105 IC onto a custom PCB following Analog Devices' layout, grounding, and thermal guidelines.
AD9460-105LVDSPCBZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Obsolete
- Number of A/D Converters:
- 1
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 105M
- Data Interface:
- Parallel
- Input Range:
- 3.4Vpp
- Power (Typ) @ Conditions:
- 1.9W @ 105MSPS
- Utilized IC / Part:
- AD9460-105
- Contents:
- Board(s)
AD9460-105LVDSPCBZ FAQ
1.How can I place an order for AD9460-105LVDSPCBZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9460-105LVDSPCBZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9460-105LVDSPCBZ reliable?
The price and inventory of AD9460-105LVDSPCBZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9460-105LVDSPCBZ is usually 5 days.
3.What payment methods are accepted for AD9460-105LVDSPCBZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9460-105LVDSPCBZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9460-105LVDSPCBZ?
AD9460-105LVDSPCBZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9460-105LVDSPCBZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9460-105LVDSPCBZ?
For technical support, including AD9460-105LVDSPCBZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9460-105LVDSPCBZ requirements.
6.How does Aetrix verify that AD9460-105LVDSPCBZ is sourced from the original manufacturer or authorized distributors?
All AD9460-105LVDSPCBZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9460-105LVDSPCBZ meets industry standards.
7.What is the process for return or replacement of AD9460-105LVDSPCBZ?
All AD9460-105LVDSPCBZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9460-105LVDSPCBZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9460-105LVDSPCBZ part is unused and in its original packaging.
Return procedure for AD9460-105LVDSPCBZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AD9460-105LVDSPCBZ Tags
-
1083
Adafruit Industries LLC
-
1085
Adafruit Industries LLC
-
ADS7038Q1EVM-PDK
Texas Instruments
-
ADS8688EVM-PDK
Texas Instruments
-
EVAL-AD7606C18FMCZ
Analog Devices Inc.
-
ADS1232REF
Texas Instruments
-
EVAL-AD4134FMCZ
Analog Devices Inc.
-
EVAL-AD7768FMCZ
Analog Devices Inc.
-
ADC128S102EVM
Texas Instruments
-
ADS124S08EVM
Texas Instruments
-
ADC6140EVM-PDK
Texas Instruments
-
ADS7066EVM-PDK
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
