Analog Devices Inc. AD9460-80LVDS/PCBZ
- Part No.:
- AD9460-80LVDS/PCBZ
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
AD9460-80LVDS/PCBZ.pdf
- Description:
- BOARD EVALUATION AD9460-80
- Quantity:
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Product details
Overview
AD9460-80LVDS/PCBZ from Analog Devices is a 16-bit, 80 MSPS analog-to-digital converter with LVDS outputs, on-chip track-and-hold, internal reference, and 615 MHz analog bandwidth. It delivers 78.4 dBFS SNR at 10 MHz input and 76.8 dBFS at 170 MHz input (3.4 Vp-p, 80 MSPS), targeting high-fidelity IF sampling in radar and MRI receivers.
For engineers reviewing the AD9460-80LVDS/PCBZ datasheet, AD9460-80LVDS/PCBZ pinout, AD9460-80LVDS/PCBZ application, or AD9460-80LVDS/PCBZ equivalent, this evaluation board enables rapid validation of LVDS-mode timing, SFDR optimization via SFDR pin control, out-of-range detection, and DCS-enabled jitter reduction in baseband and IF signal chains.
Technical Context
The AD9460-80LVDS/PCBZ implements a pipeline ADC architecture with integrated clock duty cycle stabilizer (DCS) and buffered differential analog inputs. Its 13-cycle pipeline latency and 60 fsrms aperture jitter support precise time-domain sampling for wideband applications.
It supports dual-supply operation (3.3 V AVDD1, 5.0 V AVDD2) and configurable output modes (LVDS or CMOS), with selectable data format (offset binary/twos complement) and input range (2.0–4.0 Vp-p). The SFDR pin allows front-end tuning for <200 MHz or >200 MHz analog input frequencies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit - Full ENOB preservation up to 170 MHz input frequency |
| Sampling Rate | 80 MSPS - Guaranteed maximum conversion rate with full AC performance |
| SNR @ 10 MHz | 78.4 dBFS - Enables high-dynamic-range digitization of narrowband signals |
| SFDR @ 10 MHz | 91 dBc - Suppresses spurious content critical for multicarrier receiver linearity |
| Analog Bandwidth | 615 MHz - Supports direct sampling of IF signals up to 225 MHz with minimal roll-off |
| Aperture Jitter | 60 fsrms - Limits sampling uncertainty to ≤0.03° phase error at 225 MHz |
| Input Range | 3.4 Vp-p differential - Matches standard transformer-coupled RF front ends |
Pinout & Package
AD9460-80LVDS/PCBZ is mounted on a 100-lead TQFP_EP (exposed paddle) package, Pb-free, rated for −40°C to +85°C. The evaluation board exposes all critical signals including LVDS data pairs (D0± to D15±), DCO±, CLK±, VIN±, and configuration pins (DCS MODE, OUTPUT MODE, SFDR).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK+, CLK− | Differential clock input | Accepts low-voltage differential clock; DCS stabilizes duty cycle over wide pulse-width variation |
| VIN+, VIN− | Differential analog input | High-impedance buffered input; 615 MHz bandwidth supports direct IF sampling |
| D0+ to D15+ | LVDS true data outputs | ANSI-644-compliant; 16-bit parallel LVDS bus reduces EMI vs. CMOS at 80 MSPS |
| DCO+, DCO− | Data clock output | Synchronized LVDS clock for reliable capture by FPGA/ASIC deserializers |
| SFDR | Front-end optimization control | AGND connection optimizes SFDR for <200 MHz inputs; AVDD1 for >200 MHz |
| OR+, OR− | Out-of-range indicator | Differential LVDS flag signaling input saturation-enables real-time AGC feedback |
Key Features
| Feature | Design Value |
|---|---|
| On-chip reference | 1.7 V internal trimmed reference eliminates external REF circuitry for 3.4 Vp-p input scaling |
| DCS (Duty Cycle Stabilizer) | Maintains ADC performance across clock duty cycles from 30% to 70%, relaxing clock source requirements |
| Configurable output mode | Single-pin OUTPUT MODE selection between LVDS (low noise, high speed) and CMOS (low power, short traces) |
| Out-of-range detection | Differential OR+ / OR− LVDS outputs provide immediate saturation alert without software polling |
| Thermal management | Exposed paddle soldered to AGND plane achieves θJA = 19.8°C/W-critical for sustained 1.8 W LVDS operation |
Applications
| Radar IF Digitization | MRI Signal Acquisition |
|---|---|
Use Scenario: Digitizing 70–170 MHz IF outputs from heterodyne radar receivers under high dynamic range conditions. IC Role / Device Role / Timing Role: High-linearity ADC capturing pulsed Doppler waveforms with minimal harmonic distortion. Use Value: 76.8 dBFS SNR at 170 MHz enables detection of weak return signals buried in clutter. |
Use Scenario: Sampling quadrature baseband signals from MRI gradient coil amplifiers and RF receive chains. IC Role / Device Role / Timing Role: Precision digitizer preserving phase coherence and amplitude fidelity across multi-channel arrays. Use Value: ±3.0 LSB INL and 60 fsrms jitter ensure accurate image reconstruction without spatial distortion. |
| Cellular Base Station Receiver | Communications Test Equipment |
Use Scenario: Multicarrier, multimode cellular receiver front end handling LTE/WCDMA/5G NR signals simultaneously. IC Role / Device Role / Timing Role: Wideband ADC supporting adjacent channel rejection and intermodulation suppression. Use Value: 90 dBFS two-tone SFDR at 139/140 MHz prevents cross-carrier interference in dense spectrum environments. |
Use Scenario: High-accuracy signal analyzer or arbitrary waveform generator calibration path. IC Role / Device Role / Timing Role: Reference-grade digitizer validating spectral purity and modulation accuracy. Use Value: 78.4 dBFS SNR at 10 MHz provides >12.8 ENOB for traceable metrology-grade measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9461-80EBZ | Same 16-bit, 80 MSPS core but with CMOS-only outputs and no LVDS option | Lacks LVDS drive strength and common-mode noise immunity; requires external termination | Select when system uses short PCB traces and FPGA inputs lack LVDS receivers |
| ADS5463IPFP | 16-bit, 500 MSPS, 3.3 V only, no internal reference, higher power (3.2 W) | Supports direct RF sampling >200 MHz but demands external reference, driver, and clock conditioning | Select for ultra-wideband applications where 80 MSPS is insufficient, accepting added design complexity |
Compared with AD9460-80LVDS/PCBZ, AD9461-80EBZ trades LVDS noise immunity for simpler interfacing, while ADS5463IPFP extends bandwidth at the cost of power, external components, and layout sensitivity-making AD9460-80LVDS/PCBZ optimal for balanced IF sampling with minimal BOM and layout overhead.
Availability
AD9460-80LVDS/PCBZ is available at Aetrix Electronics and suitable for radar development, MRI subsystem integration, and communications test equipment requiring stable component supply and validated reference designs.
Supply support for AD9460-80LVDS/PCBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving precision instrumentation, industrial automation, and communications markets since 1965.
The AD9460 product line delivers high-resolution, high-speed ADCs optimized for demanding IF and baseband digitization in medical imaging, defense radar, and wireless infrastructure-prioritizing SNR, SFDR, and ease of use over raw speed alone.
FAQ
What is the primary function of the AD9460-80LVDS/PCBZ evaluation board?
The AD9460-80LVDS/PCBZ is an evaluation platform for the AD9460-80LVDS analog-to-digital converter. It provides fully routed LVDS signal paths, configurable power supplies, and accessible test points to validate timing margins, SFDR optimization, DCS functionality, and out-of-range behavior-accelerating design-in of the AD9460-80LVDS in radar, MRI, and communications systems.
Does AD9460-80LVDS/PCBZ support both LVDS and CMOS output modes?
No-the AD9460-80LVDS/PCBZ is configured specifically for LVDS operation. While the underlying AD9460-80LVDS IC supports both LVDS and CMOS outputs via the OUTPUT MODE pin, this evaluation board populates only LVDS termination networks and biasing. To evaluate CMOS mode, a different board (e.g., AD9460-80CMOS/PCBZ) or custom modification is required.
How does the SFDR pin affect performance on AD9460-80LVDS/PCBZ?
On AD9460-80LVDS/PCBZ, the SFDR pin is pre-configured to AGND per default layout, optimizing spurious-free dynamic range for analog input frequencies below 200 MHz. For inputs above 200 MHz, users must re-route or jumper SFDR to AVDD1-increasing AVDD2 current by ~70 mW-to shift front-end biasing and maximize SFDR at higher frequencies.
What clock jitter specification applies to AD9460-80LVDS/PCBZ operation?
The AD9460-80LVDS/PCBZ inherits the AD9460-80LVDS IC's 60 fsrms aperture jitter specification. This value reflects total sampling uncertainty-including internal ADC jitter and external clock contribution-when using the board's recommended low-phase-noise clock source and proper layout practices per the user guide.
Is thermal management addressed on the AD9460-80LVDS/PCBZ board?
Yes-the AD9460-80LVDS/PCBZ board implements thermal best practices: the AD9460-80LVDS IC's exposed paddle is soldered directly to a large internal AGND plane, and multiple thermal vias connect top/bottom layers. This achieves effective θJA ≈ 20°C/W, enabling continuous 1.8 W operation at 80 MSPS without forced airflow.
AD9460-80LVDS/PCBZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Obsolete
- Number of A/D Converters:
- 1
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 80M
- Data Interface:
- Parallel
- Input Range:
- 3.4Vpp
- Power (Typ) @ Conditions:
- 1.7W @ 80MSPS
- Utilized IC / Part:
- AD9460-80
- Contents:
- Board(s)
AD9460-80LVDS/PCBZ FAQ
1.How can I place an order for AD9460-80LVDS/PCBZ through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9460-80LVDS/PCBZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9460-80LVDS/PCBZ reliable?
The price and inventory of AD9460-80LVDS/PCBZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9460-80LVDS/PCBZ is usually 5 days.
3.What payment methods are accepted for AD9460-80LVDS/PCBZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9460-80LVDS/PCBZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9460-80LVDS/PCBZ?
AD9460-80LVDS/PCBZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9460-80LVDS/PCBZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9460-80LVDS/PCBZ?
For technical support, including AD9460-80LVDS/PCBZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9460-80LVDS/PCBZ requirements.
6.How does Aetrix verify that AD9460-80LVDS/PCBZ is sourced from the original manufacturer or authorized distributors?
All AD9460-80LVDS/PCBZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9460-80LVDS/PCBZ meets industry standards.
7.What is the process for return or replacement of AD9460-80LVDS/PCBZ?
All AD9460-80LVDS/PCBZ units undergo pre-shipment inspection (PSI). If there is an issue with AD9460-80LVDS/PCBZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9460-80LVDS/PCBZ part is unused and in its original packaging.
Return procedure for AD9460-80LVDS/PCBZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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