Analog Devices Inc. AD9460BSVZ-105

Overview

AD9460BSVZ-105 from Analog Devices is a 16-bit, 105 MSPS monolithic pipeline analog-to-digital converter optimized for high-fidelity signal acquisition in instrumentation, radar receivers, and MRI systems. It delivers 77.2 dBFS SNR and 84 dBc SFDR at 170 MHz input with 3.4 V_p-p differential input, operates from 3.3 V and 5.0 V supplies, and features LVDS or CMOS outputs with selectable data format.

For engineers reviewing the AD9460BSVZ-105 datasheet, AD9460BSVZ-105 pinout, AD9460BSVZ-105 application, or AD9460BSVZ-105 equivalent, key selection criteria include guaranteed 105 MSPS sampling rate, 60 fs_rms aperture jitter, 100-lead TQFP_EP package with exposed heat sink, and configurable SFDR optimization via the SFDR pin for <200 MHz or >200 MHz analog input bands.

Technical Context

The AD9460BSVZ-105 implements a 16-bit pipeline ADC architecture with on-chip track-and-hold, internal 1.7 V reference (3.4 V_p-p full-scale), and clock duty cycle stabilizer (DCS) to maintain performance across wide input clock duty cycles. Its analog input bandwidth is 615 MHz, supporting baseband and IF sampling up to 225 MHz.

Dual-supply operation (AVDD1 = 3.3 V, AVDD2 = 5.0 V) separates analog core and front-end biasing, while DRVDD = 3.3 V powers digital outputs. Output modes are selected via OUTPUT MODE pin, and data format (offset binary/twos complement) is controlled by DFS pin - both CMOS-compatible logic inputs.

Key Specifications

Pinout & Package

AD9460BSVZ-105 is housed in a Pb-free, 100-lead TQFP_EP (Thin Quad Flat Package with Exposed Pad) measuring 14 mm × 14 mm × 1.4 mm, specified for −40°C to +85°C operation. The exposed heat sink must be soldered to AGND for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9461BCPZ-105, AD9460BSVZ-105 offers superior thermal performance via its soldered exposed pad and higher SFDR at 170 MHz; compared with ADS5463IPFP, it provides integrated reference, DCS, and lower power at the cost of maximum sample rate and bandwidth - making it optimal for IF-sampling radar and medical imaging.

Availability

AD9460BSVZ-105 is available at Aetrix Electronics and suitable for MRI receivers, radar signal acquisition, multicarrier cellular infrastructure, and communications instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for AD9460BSVZ-105 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9460 product line delivers high-resolution, high-speed ADCs designed specifically for demanding instrumentation, medical imaging, and defense electronics applications where SNR, SFDR, and timing precision are critical.

FAQ

What is the guaranteed maximum sampling rate for the AD9460BSVZ-105?

The AD9460BSVZ-105 is guaranteed to operate at a maximum conversion rate of 105 MSPS across the full industrial temperature range (−40°C to +85°C), as confirmed in Table 4 of the datasheet. This rate is distinct from the AD9460BSVZ-80 variant, which is rated for 80 MSPS. The AD9460BSVZ-105 maintains specified AC performance - including SNR and SFDR - only when operated at or below this guaranteed rate.

Does the AD9460BSVZ-105 require an external reference voltage?

No, the AD9460BSVZ-105 includes an internal trimmed 1.7 V reference that supports a 3.4 V_p-p differential analog input range when the SENSE pin is tied to AGND. An external reference may be used by connecting SENSE to AVDD1, but it is not required. The VREF, REFT, and REFB pins facilitate decoupling and differential reference routing, and the internal reference eliminates need for external precision references in most applications.

How does the SFDR pin affect power consumption in the AD9460BSVZ-105?

When the SFDR pin is connected to AVDD1 (for analog inputs >200 MHz), AVDD2 supply current increases by approximately 20 mW relative to the AGND-connected state (optimized for <200 MHz). This increase is explicitly documented in the Pin Function Descriptions section for the AD9460BSVZ-105. The adjustment targets front-end biasing to improve harmonic suppression at higher input frequencies, with no impact on AVDD1 or DRVDD current.

What is the purpose of the DCS MODE pin on the AD9460BSVZ-105?

DCS MODE enables or disables the on-chip Clock Duty Cycle Stabilizer. When pulled low to AGND, DCS corrects non-50% duty cycle clock inputs to preserve ADC performance - particularly SNR and SFDR - across wide variations in clock source quality. Disabling DCS (by pulling high to AVDD1) reduces power slightly but risks degraded performance with asymmetric clocks. The feature is unique to the AD9460 family and directly addresses real-world clock distribution challenges.

Can the AD9460BSVZ-105 operate with CMOS and LVDS outputs simultaneously?

No, the AD9460BSVZ-105 supports only one output interface mode at a time, selected by the OUTPUT MODE pin: logic low for CMOS, logic high for LVDS. Both modes drive the same D0+ to D15+ pins, but with different voltage levels and termination requirements. Attempting simultaneous use would violate absolute maximum ratings and cause undefined behavior. The datasheet provides separate timing diagrams and loading specifications for each mode, confirming exclusive operation.