Analog Devices Inc. AD9460BSVZ-80

Overview

AD9460BSVZ-80 from Analog Devices is a 16-bit, 80 MSPS monolithic pipeline analog-to-digital converter optimized for high-fidelity signal acquisition in instrumentation, radar receivers, and MRI systems. It delivers 78.4 dBFS SNR at 10 MHz input, 76.8 dBFS SNR at 170 MHz input (3.4 V_p-p), and 60 fs_rms aperture jitter, operating from 3.3 V and 5.0 V supplies with LVDS or CMOS outputs.

For engineers reviewing the AD9460BSVZ-80 datasheet, AD9460BSVZ-80 pinout, AD9460BSVZ-80 application, or AD9460BSVZ-80 equivalent, key selection considerations include its guaranteed 80 MSPS sampling rate, differential 3.4 V_p-p full-scale input range, on-chip track-and-hold, clock duty cycle stabilizer (DCS), and out-of-range (OR) flag output - all in a Pb-free 100-lead TQFP_EP package rated for −40°C to +85°C.

Technical Context

The AD9460BSVZ-80 implements a 16-bit pipeline ADC architecture with integrated track-and-hold, buffered differential analog inputs, and selectable output modes (LVDS or CMOS). Its clock duty cycle stabilizer maintains performance across wide input clock duty cycle variations, while the SFDR control pin enables analog front-end optimization for input frequencies below or above 200 MHz.

It supports dual reference configurations (internal 1.7 V or external), offers offset binary or twos complement data formatting, and provides a dedicated data capture clock (DCO±) with 13-cycle pipeline latency. The device requires no external reference or driver components in many applications, simplifying system design for high-speed IF sampling.

Key Specifications

Pinout & Package

The AD9460BSVZ-80 is housed in a Pb-free, 100-lead TQFP_EP (exposed pad) package, thermally optimized with θ_JA = 19.8°C/W when the heat sink is soldered to AGND. Pin functions are mode-dependent (LVDS vs. CMOS); unused pins are designated DNC and must float.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9460BSVZ-105 and AD9643BCPZ-250, the AD9460BSVZ-80 uniquely balances 16-bit precision, 80 MSPS throughput, and 60 fs_rms jitter in a thermally robust TQFP_EP package - making it optimal for medical imaging and radar IF digitization where SNR and phase stability dominate over peak sample rate.

Availability

AD9460BSVZ-80 is available at Aetrix Electronics and suitable for MRI receivers, radar IF digitization, antenna array beamforming, and power amplifier linearization requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for AD9460BSVZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, headquartered in Norwood, MA.

The AD9460 product line delivers high-resolution, high-speed ADCs optimized for demanding instrumentation, medical imaging, and defense radar applications where signal fidelity and timing integrity are paramount.

FAQ

What is the guaranteed maximum sampling rate for the AD9460BSVZ-80?

The AD9460BSVZ-80 is guaranteed to operate at a maximum sampling rate of 80 MSPS across the full industrial temperature range (−40°C to +85°C), with AC specifications including SNR and SFDR validated at this rate per Table 4 in the datasheet. This is distinct from the AD9460BSVZ-105 variant, which guarantees 105 MSPS.

Does the AD9460BSVZ-80 require an external reference voltage?

No, the AD9460BSVZ-80 includes an internal trimmed 1.7 V reference that supports a 3.4 V_p-p differential analog input range when the SENSE pin is tied to AGND. An external reference may be used by connecting SENSE to AVDD1, but it is not required for standard operation.

How does the clock duty cycle stabilizer (DCS) function in the AD9460BSVZ-80?

The DCS in the AD9460BSVZ-80 actively corrects input clock duty cycle deviations, maintaining optimal ADC performance even with non-50% duty cycle clocks (e.g., from PLL dividers). When DCS MODE is pulled low to AGND, the circuit adjusts internal timing to minimize aperture uncertainty - directly preserving the specified 60 fs_rms jitter.

What is the purpose of the SFDR pin on the AD9460BSVZ-80?

The SFDR pin on the AD9460BSVZ-80 configures the analog front-end for optimal spurious-free dynamic range: tie to AGND for analog input frequencies <200 MHz (e.g., radar IF), or to AVDD1 for >200 MHz (e.g., broadband wireless). This setting adjusts bias currents, trading ~70 mW AVDD2 power for improved SFDR above 200 MHz.

Can the AD9460BSVZ-80 interface directly with an FPGA using LVDS outputs?

Yes, the AD9460BSVZ-80 provides ANSI-644-compliant LVDS outputs (D0± to D15± and DCO±) with 247–545 mV differential output voltage and 1.125–1.375 V common-mode offset. These meet standard FPGA LVDS receiver thresholds and require only 100 Ω differential termination per pair, enabling direct connection without level-shifting.