Analog Devices Inc. AD9517-2BCPZ

Overview

AD9517-2BCPZ from Analog Devices is a 12-output clock generator with integrated 2.2 GHz VCO, delivering subpicosecond jitter performance for high-speed data converter timing. It features four 1.6 GHz LVPECL outputs (in two pairs), four 800 MHz LVDS outputs (in two pairs, each reconfigurable as dual 250 MHz CMOS), programmable dividers, and fine delay adjustment on all LVDS/CMOS outputs. It is used in 10/40/100 GbE line cards and high-performance ADC/DAC clocking.

For engineers reviewing the AD9517-2BCPZ datasheet, AD9517-2BCPZ pinout, AD9517-2BCPZ application, or AD9517-2BCPZ equivalent, this page provides verified specifications, package mapping, output synchronization behavior, additive jitter values (225 fs rms LVPECL, 275 fs rms LVDS), and real-world timing role in SONET, Synchronous Ethernet, and data converter systems.

Technical Context

The AD9517-2BCPZ implements a low-noise PLL with an on-chip VCO tunable from 2.05 GHz to 2.33 GHz and supports external VCO/VCXO up to 2.4 GHz. Its phase-frequency detector operates at up to 100 MHz with selectable antibacklash pulse widths (1.3 ns to 6.0 ns) and digital lock detect with configurable window thresholds.

Each of the two LVPECL output pairs shares a 1-to-32 divider with coarse phase delay; each LVDS pair uses two cascaded 1-to-32 dividers enabling division up to 1024. All outputs support automatic power-up synchronization and manual resync, with channel-to-channel skew <10 ps for paired LVPECL outputs and <62 ps for paired LVDS outputs.

Key Specifications

Pinout & Package

The AD9517-2BCPZ is housed in a 48-lead LFCSP (7 mm × 7 mm, 0.5 mm pitch) with exposed paddle for thermal management. Pin functions are defined per Analog Devices' AD9517-2 Rev. F datasheet, Page 18.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generation applications.

Compared with AD9517-2BCPZ, AD9516-2BCPZ reduces output count but retains identical jitter and VCO performance in smaller footprint, while LMK04832RHAT trades 65 fs higher additive jitter for EEPROM configurability and dual-loop flexibility - making AD9517-2BCPZ optimal for fixed-configuration, ultra-low-jitter ADC/DAC timing.

Availability

AD9517-2BCPZ is available at Aetrix Electronics and suitable for 10/40/100 GbE networking, high-speed data acquisition, and wireless infrastructure applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for AD9517-2BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The AD9517 product line delivers ultra-low-jitter clock generation for data converters and high-speed serial interfaces, emphasizing phase noise optimization, deterministic synchronization, and flexible output configuration in compact packages.

FAQ

What is the maximum operating frequency of the AD9517-2BCPZ's on-chip VCO?

The AD9517-2BCPZ's on-chip VCO tunes from 2.05 GHz to 2.33 GHz, as specified in the Rev. F datasheet Table 2. This range supports direct synthesis of sampling clocks for 12-bit to 16-bit ADCs operating up to 1.1 GSPS and enables clean multiplication of common reference frequencies like 122.88 MHz and 156.25 MHz. Operation outside this band requires an external VCO/VCXO.

Can the AD9517-2BCPZ generate both LVPECL and LVDS outputs simultaneously?

Yes, the AD9517-2BCPZ simultaneously drives four LVPECL outputs (OUT0–OUT3) and four LVDS outputs (OUT4–OUT7) from independent divider paths. Each LVDS output can also be reconfigured as two 250 MHz CMOS outputs, allowing up to 12 distinct clock domains. Power sequencing and supply isolation (VS_LVPECL separate from VS) ensure signal integrity across mixed-output operation.

Does the AD9517-2BCPZ support automatic synchronization of all outputs at power-up?

Yes, the AD9517-2BCPZ performs automatic synchronization of all outputs on power-up, establishing deterministic phase relationships across all 12 outputs without host processor intervention. This behavior is hardware-enforced and documented in the "Automatic Synchronization" section (Page 1). Manual resync via the SYNC pin is also supported for runtime recalibration.

What is the additive output jitter specification for AD9517-2BCPZ LVPECL outputs?

The AD9517-2BCPZ specifies 225 fs rms additive output jitter for its LVPECL outputs under distribution-only conditions (VCO divider bypassed), per Table 6 of the Rev. F datasheet. This value excludes PLL and VCO contributions and reflects pure distribution path noise - critical for maintaining SNR in high-resolution ADCs where jitter directly degrades effective number of bits.

Is the AD9517-2BCPZ pin-compatible with other members of the AD9517 family?

No, the AD9517-2BCPZ is not pin-compatible with AD9517-0, -1, -3, or -4 variants. While all share the same 48-lead LFCSP package, pin functions differ significantly - for example, the AD9517-0 lacks LVDS outputs entirely and routes additional control signals to pins used for OUT4–OUT7 on the AD9517-2BCPZ. Board-level redesign is required for substitution.