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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. AD9572ACPZPEC-R7

Name: AD9572ACPZPEC-R7
Brand: Analog Devices Inc.
SKU: AD9572ACPZPEC-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9572ACPZPEC-R7

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 40-WFQFN Exposed Pad, CSP

Datasheet:: AD9572ACPZPEC-R7.pdf

Description:: IC CLOCK GENERATOR 40LFCSP

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Product details

Overview

AD9572ACPZPEC-R7 from Analog Devices is a dual-PLL, 7-output clock generator IC optimized for fiber channel and Gigabit Ethernet line cards. It delivers seven synchronized clock outputs-including 1 × 156.25 MHz, 2 × 106.25 MHz, 2 × 100/125 MHz (strappable), 1 × 33.33 MHz CMOS, and 1 × 25 MHz CMOS-using a single 25 MHz crystal input. Its 0.22 ps rms jitter (12 kHz–20 MHz, 106.25 MHz LVDS) and −217.5 dBc/Hz PLL figure of merit support low-phase-noise timing in high-speed serial interfaces.

For engineers reviewing the AD9572ACPZPEC-R7 datasheet, AD9572ACPZPEC-R7 pinout, AD9572ACPZPEC-R7 application, or AD9572ACPZPEC-R7 equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/CMOS), strappable frequency selection (100/125 MHz), integrated loop filters, 40-lead 6 mm × 6 mm LFCSP packaging, and guaranteed operation from −40°C to +85°C.

Technical Context

The AD9572ACPZPEC-R7 integrates two independent integer-N PLL cores: one optimized for Fibre Channel (FC) at 156.25 MHz with dedicated VCO and feedback divider, and another for Gigabit Ethernet (GbE) supporting 106.25 MHz and 100/125 MHz outputs. Each PLL includes a low-noise PFD, precision charge pump, third-order integrated loop filter, and preprogrammed dividers-eliminating external passive components.

Output drivers are configurable via strapping pins: FREQSEL selects between 100 MHz and 125 MHz on Pins 19/20/21/22; REFSEL chooses crystal or external REFCLK input; FORCE_LOW forces the 33.33 MHz output low. All outputs are electrically isolated with dedicated VS supply pins per functional block to minimize crosstalk and power-supply-induced jitter.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	7 independent clocks: 1×156.25 MHz, 2×106.25 MHz, 2×100/125 MHz (strappable), 1×33.33 MHz CMOS, 1×25 MHz CMOS
Jitter (106.25 MHz LVDS)	0.22 ps rms (637 kHz–10 MHz band); enables PCIe Gen2/Gen3 reference clock compliance
Phase Noise (156.25 MHz LVDS)	−152 dBc/Hz at 10 MHz offset; supports <10⁻¹² BER in 10G FC links
Input Reference	25 MHz fundamental-mode crystal (14 pF load, 50 Ω ESR) or CMOS clock; no external oscillator required
Supply & Power	Single 3.3 V supply; 715 mW (LVDS mode), 1075 mW (LVPECL mode); thermal resistance θJA = 27.5°C/W
Package	40-lead, 6 mm × 6 mm LFCSP with exposed grounded paddle; RoHS-compliant, moisture sensitivity level 3
Operating Temp	−40°C to +85°C ambient; qualified for industrial and telecom infrastructure use

Pinout & Package

AD9572ACPZPEC-R7 uses a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP) with an exposed thermal/electrical paddle that must be soldered to PCB ground. Pin 1 is marked by a dot; the paddle is electrically connected to GND and critical for thermal performance and signal integrity.

Pin/Terminal	Circuit Role	Design Meaning
1, 10, 34, EPAD	GND	System ground reference; EPAD must be soldered to solid ground plane for thermal dissipation and noise reduction
4, 23	25M / 33M	Single-ended CMOS outputs; 25 MHz (buffered crystal ref), 33.33 MHz (FC-derived); 1.0 mA drive, 0.1–3.2 V swing
6, 7	XO	Differential crystal connection; accepts 25 MHz fundamental-mode crystal with 14 pF load capacitance
8	REFCLK	25 MHz CMOS reference input; tied low when crystal used; 2.0 V logic-high threshold
9, 27, 37	REFSEL / FREQSEL / FORCE_LOW	Strap pins: REFSEL selects ref source; FREQSEL configures 100/125 MHz; FORCE_LOW disables 33M output
17–18, 19–22, 29–32	156M / 100M/125M / 106M	Differential LVPECL/LVDS outputs; each pair requires 100 Ω diff termination (LVDS) or 200 Ω to GND (LVPECL)
14, 36	BYPASS1 / BYPASS2	LDO bypass pins; require 220 nF ceramic capacitors to GND for stable internal regulation

Key Features

Feature	Design Value
Dual independent PLLs	Separate FC (156.25 MHz) and GbE (106.25/100/125 MHz) synthesis paths prevent inter-modulation and enable concurrent protocol support
Integrated loop filters	Third-order active filters embedded per PLL eliminate 12+ external passives, reducing BOM count and layout area by >30%
Output format selection	Hardware-strapped LVPECL or LVDS per output group; avoids level-shifter ICs and simplifies interface to SerDes PHYs
Low additive jitter	0.19 ps rms (1.875–20 MHz, 156.25 MHz LVDS) ensures minimal contribution to total system jitter budget in multi-stage clock trees
Dedicated supply domains	12 distinct VS pins isolate analog PLL, digital logic, and output buffers-reducing supply-induced crosstalk below −70 dB
Crystal oscillator interface	On-chip oscillator circuit with 14 pF load tuning supports direct 25 MHz crystal connection without external caps or buffers

Applications

Fibre Channel Line Cards	Gigabit Ethernet Switches
Use Scenario: 16-port Fibre Channel ASIC requiring synchronous 156.25 MHz reference for 10G FC links and 25 MHz for management interface. IC Role / Device Role / Timing Role: Primary clock synthesizer generating all domain clocks from single crystal; provides jitter-clean 156.25 MHz to FC transceivers and 25 MHz to baseband controller. Use Value: Eliminates need for multiple discrete oscillators and reduces board space by 40% versus discrete clock tree solutions.	Use Scenario: Quad-SFP+ Ethernet switch fabric with mixed 100/125 MHz PHY requirements across ports. IC Role / Device Role / Timing Role: Strappable 100/125 MHz output generator enabling single hardware design to support both IEEE 802.3ae and 802.3an standards. Use Value: Reduces SKU count and inventory complexity while maintaining <0.5 ps added jitter margin for 10GBASE-R compliance.
PCIe Gen2/Gen3 Root Complex	Optical Transport Network (OTN) Cards
Use Scenario: Server motherboard requiring PCIe reference clocks (100 MHz) and auxiliary 106.25 MHz for SATA/SAS controllers. IC Role / Device Role / Timing Role: Multi-frequency clock source delivering PCIe-compliant 100 MHz (LVDS) and 106.25 MHz (LVPECL) simultaneously with shared 25 MHz reference. Use Value: Meets PCIe Gen3 jitter spec (1.0 ps rms, 12 kHz–20 MHz) with 0.44 ps typical margin at 100 MHz LVDS output.	Use Scenario: OTN line card needing 156.25 MHz for SONET OC-192 and 33.33 MHz for framing logic. IC Role / Device Role / Timing Role: Dual-PLL timing engine providing SONET-compliant 156.25 MHz (−152 dBc/Hz @ 10 MHz) and low-skew 33.33 MHz CMOS for TDM mapping. Use Value: Achieves <0.1 ppm frequency accuracy over temperature, meeting GR-253-CORE stability requirements for carrier-grade systems.

Fibre Channel Line Cards

Gigabit Ethernet Switches

Use Scenario: 16-port Fibre Channel ASIC requiring synchronous 156.25 MHz reference for 10G FC links and 25 MHz for management interface.

IC Role / Device Role / Timing Role: Primary clock synthesizer generating all domain clocks from single crystal; provides jitter-clean 156.25 MHz to FC transceivers and 25 MHz to baseband controller.

Use Value: Eliminates need for multiple discrete oscillators and reduces board space by 40% versus discrete clock tree solutions.

Use Scenario: Quad-SFP+ Ethernet switch fabric with mixed 100/125 MHz PHY requirements across ports.

IC Role / Device Role / Timing Role: Strappable 100/125 MHz output generator enabling single hardware design to support both IEEE 802.3ae and 802.3an standards.

Use Value: Reduces SKU count and inventory complexity while maintaining <0.5 ps added jitter margin for 10GBASE-R compliance.

PCIe Gen2/Gen3 Root Complex

Optical Transport Network (OTN) Cards

Use Scenario: Server motherboard requiring PCIe reference clocks (100 MHz) and auxiliary 106.25 MHz for SATA/SAS controllers.

IC Role / Device Role / Timing Role: Multi-frequency clock source delivering PCIe-compliant 100 MHz (LVDS) and 106.25 MHz (LVPECL) simultaneously with shared 25 MHz reference.

Use Value: Meets PCIe Gen3 jitter spec (1.0 ps rms, 12 kHz–20 MHz) with 0.44 ps typical margin at 100 MHz LVDS output.

Use Scenario: OTN line card needing 156.25 MHz for SONET OC-192 and 33.33 MHz for framing logic.

IC Role / Device Role / Timing Role: Dual-PLL timing engine providing SONET-compliant 156.25 MHz (−152 dBc/Hz @ 10 MHz) and low-skew 33.33 MHz CMOS for TDM mapping.

Use Value: Achieves <0.1 ppm frequency accuracy over temperature, meeting GR-253-CORE stability requirements for carrier-grade systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9573BCPZ-REEL7	Same dual-PLL architecture but adds spread-spectrum capability and supports 25–212.5 MHz output range; higher 1.2 W LVPECL power dissipation	Targeted at EMI-sensitive systems (e.g., medical imaging); lacks 33.33 MHz CMOS output	Select AD9573 if spread-spectrum clocking is required to reduce radiated emissions; not drop-in due to different pinout and missing 33M output
Si5338A-A-GM	4-output, programmable I²C-based clock generator; 0.3 ps rms jitter (12 kHz–20 MHz); requires external configuration EEPROM	Designed for flexible, software-configurable timing in FPGA-based platforms; no native 156.25 MHz preset	Choose Si5338A for designs needing field-upgradable frequencies or >4 outputs; requires firmware integration and adds BOM cost

Compared with AD9572ACPZPEC-R7, AD9573 offers EMI reduction at the cost of fixed 33.33 MHz omission and higher power, while Si5338A trades preset simplicity for programmability and increased system-level design effort.

Availability

AD9572ACPZPEC-R7 is available at Aetrix Electronics and suitable for fiber channel line cards, Gigabit Ethernet switches, and PCIe Gen2/Gen3 root complexes requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature operation.

Supply support for AD9572ACPZPEC-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with R&D and manufacturing facilities worldwide.

The AD9572ACPZPEC-R7 belongs to Analog Devices' clock generation product line, designed specifically for low-jitter, multi-protocol timing in datacenter and telecom infrastructure where deterministic phase noise and output isolation are critical.

FAQ

What reference input options does the AD9572ACPZPEC-R7 support?

The AD9572ACPZPEC-R7 supports either a 25 MHz fundamental-mode crystal connected across Pins 6 and 7 (XO), or a 25 MHz CMOS clock applied to Pin 8 (REFCLK). REFSEL pin (Pin 9) selects between these sources. Crystal specifications require 14 pF load capacitance and ≤50 Ω ESR; external clock must meet 2.0 V logic-high and 0.8 V logic-low thresholds. The AD9572ACPZPEC-R7 contains no internal crystal driver compensation for overtone crystals.

How is output frequency selection implemented on the AD9572ACPZPEC-R7?

Frequency selection for the 100/125 MHz output pair (Pins 19/20/21/22) is controlled by the FREQSEL pin (Pin 27): logic high selects 125 MHz, logic low selects 100 MHz. This strapping is sampled at power-up and latched; dynamic reconfiguration is not supported. Other outputs-156.25 MHz, 106.25 MHz, 33.33 MHz, and 25 MHz-are fixed and cannot be altered via pins or registers. The AD9572ACPZPEC-R7 has no I²C or SPI interface.

What is the purpose of the FORCE_LOW pin on the AD9572ACPZPEC-R7?

The FORCE_LOW pin (Pin 37) is an active-high control that forces the 33.33 MHz CMOS output (Pin 23) into a static logic-low state, overriding normal clock generation. This allows deterministic shutdown of the 33M domain during system sleep modes or fault conditions without affecting other outputs. The pin has a 16 kΩ internal pull-down resistor; driving it above 2.0 V activates the force function. The AD9572ACPZPEC-R7 continues normal operation on all other outputs when FORCE_LOW is asserted.

Can the AD9572ACPZPEC-R7 generate both LVPECL and LVDS outputs simultaneously?

Yes-the AD9572ACPZPEC-R7 supports mixed output formats. Each differential output pair (156M, 100M/125M, 106M) can be configured independently for LVPECL or LVDS operation via external termination: 200 Ω to GND for LVPECL, 100 Ω differential for LVDS. Output voltage levels and drive strength automatically adapt. However, all outputs within a given group (e.g., both 106M pins) must use the same format; mixed-format per pair is not supported. The AD9572ACPZPEC-R7 datasheet specifies separate jitter and phase noise values for each format.

What thermal management is required for the AD9572ACPZPEC-R7 in continuous operation?

The AD9572ACPZPEC-R7 has a thermal resistance θJA of 27.5°C/W in a standard 4-layer PCB layout. At maximum LVPECL power dissipation (1305 mW), junction temperature rise is ~36°C above ambient-well within the 150°C absolute max. To ensure reliability, the exposed paddle (EPAD) must be soldered to a minimum 200 mm² copper pour connected to GND. No heatsink is required below 85°C ambient, but airflow >200 LFM is recommended for sustained 100% LVPECL output loading. The AD9572ACPZPEC-R7 includes no thermal shutdown circuitry.

AD9572ACPZPEC-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 40-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Generator, Fanout Distribution, Multiplexer

PLL:: Yes

Input:: Crystal

Output:: CMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 1:7

Differential - Input:Output:: No/Yes

Frequency - Max:: 156.25MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 40-LFCSP-WQ (6x6)

AD9572ACPZPEC-R7 FAQ

1.How can I place an order for AD9572ACPZPEC-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9572ACPZPEC-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9572ACPZPEC-R7 reliable?

The price and inventory of AD9572ACPZPEC-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9572ACPZPEC-R7 is usually 5 days.

3.What payment methods are accepted for AD9572ACPZPEC-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9572ACPZPEC-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9572ACPZPEC-R7?

AD9572ACPZPEC-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9572ACPZPEC-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9572ACPZPEC-R7?

For technical support, including AD9572ACPZPEC-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9572ACPZPEC-R7 requirements.

6.How does Aetrix verify that AD9572ACPZPEC-R7 is sourced from the original manufacturer or authorized distributors?

All AD9572ACPZPEC-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9572ACPZPEC-R7 meets industry standards.

7.What is the process for return or replacement of AD9572ACPZPEC-R7?

All AD9572ACPZPEC-R7 units undergo pre-shipment inspection (PSI). If there is an issue with AD9572ACPZPEC-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9572ACPZPEC-R7 part is unused and in its original packaging.

Return procedure for AD9572ACPZPEC-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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