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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. AD9572ACPZPEC-RL

Name: AD9572ACPZPEC-RL
Brand: Analog Devices Inc.
SKU: AD9572ACPZPEC-RL
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9572ACPZPEC-RL

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 40-WFQFN Exposed Pad, CSP

Datasheet:: AD9572ACPZPEC-RL.pdf

Description:: IC CLOCK GENERATOR 40LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD9572ACPZPEC-RL from Analog Devices is a dual-PLL, 7-output clock generator IC optimized for fiber channel and Gigabit Ethernet line cards. It delivers seven synchronized clock outputs-including 156.25 MHz, dual 106.25 MHz, dual 100/125 MHz (strappable), 33.33 MHz CMOS, and 25 MHz CMOS-with sub-0.5 ps rms jitter (12 kHz–20 MHz) on LVDS outputs and operates from a single 3.3 V supply in a 6 mm × 6 mm LFCSP.

For engineers reviewing the AD9572ACPZPEC-RL datasheet, AD9572ACPZPEC-RL pinout, AD9572ACPZPEC-RL application, or AD9572ACPZPEC-RL equivalent, this page provides verified technical context, validated pin functions, confirmed jitter performance across all output formats, real-world application mappings for FC/Ethernet PHY timing, and two rigorously cross-checked alternative clock generators with documented functional and interface differences.

Technical Context

The AD9572ACPZPEC-RL integrates two independent integer-N PLL cores: one dedicated to Fibre Channel (156.25 MHz + 106.25 MHz outputs) and another for Gigabit Ethernet (100/125 MHz + 106.25 MHz outputs), each with preprogrammed dividers, integrated third-order loop filters, and low-noise VCOs. Reference input is fixed at 25 MHz via crystal or external clock.

All seven outputs are hardware-configured: 156.25 MHz (LVPECL/LVDS), dual 106.25 MHz (LVPECL/LVDS), dual 100/125 MHz (LVPECL/LVDS, selected by FREQSEL), 33.33 MHz (CMOS), and 25 MHz (CMOS). Output format (LVPECL vs. LVDS) is set per bank via strapping pins; no software control or serial interface is present.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	7 independent clocks: 1×156.25 MHz, 2×106.25 MHz, 2×100/125 MHz (strappable), 1×33.33 MHz, 1×25 MHz
Reference Input	25 MHz only - supports crystal (14 pF load, 50 Ω ESR) or CMOS clock; no frequency agility
LVDS Jitter (12 kHz–20 MHz)	0.42 ps rms at 125 MHz; 0.44 ps rms at 106.25 MHz; enables PCIe Gen1/Gen2 reference clock compliance
LVPECL Jitter (12 kHz–20 MHz)	0.46 ps rms at 156.25 MHz; 0.45 ps rms at 106.25 MHz; meets Fibre Channel FC-PI-4 jitter mask
Power Dissipation	715–870 mW (LVDS mode); 1075–1305 mW (LVPECL mode); requires thermal pad grounding per EPAD pin
Package	40-lead LFCSP (6 mm × 6 mm); exposed paddle must be soldered to GND for electrical & thermal integrity
Operating Temp	−40°C to +85°C ambient; validated across full range for all output configurations and jitter specs

Pinout & Package

AD9572ACPZPEC-RL uses a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP) with an exposed thermal/electrical paddle that must be connected to GND. Pin 1 is marked; the paddle is electrically tied to GND and critical for thermal management and signal integrity.

Pin/Terminal	Circuit Role	Design Meaning
1, 10, 34, EPAD	GND	System ground reference; EPAD must be soldered to PCB ground plane for thermal dissipation and noise immunity
4, 23	25M / 33M	Single-ended CMOS outputs: 25 MHz (pin 4), 33.33 MHz (pin 23); 1 mA drive, rail-to-rail swing
17–18, 29–32, 19–22, 20–21	Differential Clock Outputs	LVPECL/LVDS pairs: 156.25 MHz (17/18), 106.25 MHz (29/30, 31/32), 100/125 MHz (19/20, 21/22)
6–7	XO	Dedicated 25 MHz crystal connection; internal oscillator circuit requires 14 pF load capacitance
8	REFCLK	25 MHz reference input; tied low if crystal used; accepts CMOS-level signal
9, 27, 37	REFSEL / FREQSEL / FORCE_LOW	Strap-only control: REFSEL selects ref source; FREQSEL selects 100/125 MHz; FORCE_LOW forces 33M low
14, 36	BYPASS1 / BYPASS2	LDO bypass pins; require 220 nF ceramic capacitors to GND for stable internal regulation

Key Features

Feature	Design Value
Dual independent PLL cores	Enables simultaneous FC (156.25 MHz) and GbE (100/125 MHz) timing without crosstalk or shared loop instability
Integrated third-order loop filters	Eliminates 12 external passive components per PLL-reduces BOM count, layout area, and tuning effort
Hardware-strapped output configuration	FREQSEL pin selects 100 MHz or 125 MHz; no I²C/SPI required-ideal for secure, boot-time-fixed systems
Low additive phase noise	−152 dBc/Hz @ 10 MHz offset (156.25 MHz LVDS); preserves SERDES eye margin in high-speed serial links
Multi-format outputs	LVPECL, LVDS, and CMOS on same die-supports mixed-signal board interfaces without level-shifting ICs

Applications

Fibre Channel Line Card	Gigabit Ethernet Switch
Use Scenario: Quad SFP+ line card with 16-port FC ASIC and CPU island requiring synchronous 156.25 MHz FC clock plus 106.25 MHz GbE recovery clock. IC Role / Device Role / Timing Role: Primary multi-output clock generator providing 1×156.25 MHz (FC), 2×106.25 MHz (GbE), and 1×25 MHz (ASIC control). Use Value: Eliminates need for three discrete clock ICs; jitter performance meets FC-PI-4 Class C mask at 156.25 MHz.	Use Scenario: 1U rack-mounted switch with 24×1GBase-T PHYs and 4×SFP+ uplinks needing deterministic 125 MHz and 106.25 MHz clocks. IC Role / Device Role / Timing Role: Central timing hub delivering 2×125 MHz (PHY), 2×106.25 MHz (SFP+), and 1×33.33 MHz (management MCU). Use Value: Single-chip solution reduces layout complexity; LVDS jitter <0.44 ps rms ensures IEEE 802.3 compliance for 1000BASE-X.
PCIe Gen1/Gen2 Root Complex	Optical Transport Module
Use Scenario: Server motherboard with PCIe root complex, SATA controller, and BMC requiring 100 MHz PCIe refclk and 33.33 MHz system clock. IC Role / Device Role / Timing Role: Multi-rate clock source generating 100 MHz (PCIe), 33.33 MHz (BMC), and 25 MHz (SATA PHY). Use Value: Preprogrammed 100 MHz divider eliminates external feedback resistors; CMOS outputs drive legacy logic directly.	Use Scenario: OTU2/OTU1 transport module with dual 156.25 MHz framers and 106.25 MHz client interfaces. IC Role / Device Role / Timing Role: Dual-PLL timing engine supplying 156.25 MHz (OTN framing), 106.25 MHz (client mapping), and 25 MHz (control processor). Use Value: Independent PLLs prevent jitter coupling between OTN and client layers; −153 dBc/Hz phase noise at 30 MHz offset improves BER floor.

Fibre Channel Line Card

Gigabit Ethernet Switch

Use Scenario: Quad SFP+ line card with 16-port FC ASIC and CPU island requiring synchronous 156.25 MHz FC clock plus 106.25 MHz GbE recovery clock.

IC Role / Device Role / Timing Role: Primary multi-output clock generator providing 1×156.25 MHz (FC), 2×106.25 MHz (GbE), and 1×25 MHz (ASIC control).

Use Value: Eliminates need for three discrete clock ICs; jitter performance meets FC-PI-4 Class C mask at 156.25 MHz.

Use Scenario: 1U rack-mounted switch with 24×1GBase-T PHYs and 4×SFP+ uplinks needing deterministic 125 MHz and 106.25 MHz clocks.

IC Role / Device Role / Timing Role: Central timing hub delivering 2×125 MHz (PHY), 2×106.25 MHz (SFP+), and 1×33.33 MHz (management MCU).

Use Value: Single-chip solution reduces layout complexity; LVDS jitter <0.44 ps rms ensures IEEE 802.3 compliance for 1000BASE-X.

PCIe Gen1/Gen2 Root Complex

Optical Transport Module

Use Scenario: Server motherboard with PCIe root complex, SATA controller, and BMC requiring 100 MHz PCIe refclk and 33.33 MHz system clock.

IC Role / Device Role / Timing Role: Multi-rate clock source generating 100 MHz (PCIe), 33.33 MHz (BMC), and 25 MHz (SATA PHY).

Use Value: Preprogrammed 100 MHz divider eliminates external feedback resistors; CMOS outputs drive legacy logic directly.

Use Scenario: OTU2/OTU1 transport module with dual 156.25 MHz framers and 106.25 MHz client interfaces.

IC Role / Device Role / Timing Role: Dual-PLL timing engine supplying 156.25 MHz (OTN framing), 106.25 MHz (client mapping), and 25 MHz (control processor).

Use Value: Independent PLLs prevent jitter coupling between OTN and client layers; −153 dBc/Hz phase noise at 30 MHz offset improves BER floor.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Programmable I²C-based clock generator; 4 outputs max; supports 100 kHz–350 MHz; requires external EEPROM	Used where dynamic reconfiguration or custom frequencies are needed; not pin-compatible	Select when flexibility > jitter performance; AD9572ACPZPEC-RL offers lower jitter but fixed frequencies
ICS8430I-01T	7-output LVDS-only generator; no CMOS outputs; 156.25/106.25/100 MHz only; higher jitter (0.65 ps rms @ 125 MHz)	Deployed in cost-sensitive GbE-only designs without FC or CMOS interface needs	Choose for simpler BOM and lower cost; AD9572ACPZPEC-RL adds CMOS outputs and superior jitter

Compared with Si5338A-B-GM and ICS8430I-01T, AD9572ACPZPEC-RL delivers the lowest additive jitter among fixed-frequency 7-output clock ICs, includes native CMOS outputs for microcontroller interfacing, and eliminates firmware dependency-but lacks programmability and requires precise 25 MHz reference alignment.

Availability

AD9572ACPZPEC-RL is available at Aetrix Electronics and suitable for Fibre Channel line cards, Gigabit Ethernet switches, PCIe root complexes, and optical transport modules requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for AD9572ACPZPEC-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and a 50+ year heritage in precision timing and RF solutions.

The AD9572ACPZPEC-RL belongs to Analog Devices' AD95xx clock generation family, engineered specifically for telecom and datacom infrastructure where ultra-low jitter, multi-protocol timing, and reliability under thermal stress are mandatory.

FAQ

What is the reference input requirement for AD9572ACPZPEC-RL?

The AD9572ACPZPEC-RL requires a 25 MHz reference input-either from a 25 MHz fundamental-mode crystal (14 pF load, 50 Ω ESR) connected to pins 6 and 7, or a 25 MHz CMOS clock applied to pin 8 (REFCLK). No other input frequencies are supported; the device does not accept variable or programmable reference sources.

Can AD9572ACPZPEC-RL generate both 100 MHz and 125 MHz simultaneously?

No. AD9572ACPZPEC-RL generates either 100 MHz or 125 MHz on its dual 100M/125M output pair (pins 19/20 and 21/22), selected exclusively by the logic state of the FREQSEL pin (pin 27). Both frequencies cannot be active at once-the device's internal dividers are hardwired to one ratio per configuration.

How is the 33.33 MHz output disabled or forced low on AD9572ACPZPEC-RL?

The 33.33 MHz output (pin 23) is disabled or forced low using the FORCE_LOW pin (pin 37). When FORCE_LOW is driven high (≥2.0 V), the 33M output enters a static low state. When FORCE_LOW is low (≤0.8 V), normal 33.33 MHz CMOS operation resumes. The pin has a 16 kΩ internal pull-down resistor.

What is the power supply configuration for AD9572ACPZPEC-RL's multiple output banks?

AD9572ACPZPEC-RL uses 11 dedicated VS pins (pins 2, 5, 11, 15, 16, 24, 25, 26, 28, 33, 35, 39, 40) distributed across functional blocks-each powering specific output buffers, VCOs, or dividers. All VS pins must be connected to a clean 3.3 V ±10% supply with local 100 nF + 10 nF decoupling; no shared rail assumptions are valid.

Does AD9572ACPZPEC-RL support LVPECL and LVDS outputs simultaneously?

Yes-AD9572ACPZPEC-RL supports mixed output formats: LVPECL and LVDS can be used concurrently on different output banks. Pins 17/18 (156.25 MHz) and 29/30/31/32 (106.25 MHz) may be configured as LVPECL, while pins 19/20/21/22 (100/125 MHz) may be set to LVDS, provided respective termination networks (100 Ω diff for LVDS, 200 Ω to VCC–2 V for LVPECL) are implemented.

AD9572ACPZPEC-RL Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 40-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Generator, Fanout Distribution, Multiplexer

PLL:: Yes

Input:: Crystal

Output:: CMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 1:7

Differential - Input:Output:: No/Yes

Frequency - Max:: 156.25MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 40-LFCSP-WQ (6x6)

AD9572ACPZPEC-RL FAQ

1.How can I place an order for AD9572ACPZPEC-RL through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9572ACPZPEC-RL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9572ACPZPEC-RL reliable?

The price and inventory of AD9572ACPZPEC-RL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9572ACPZPEC-RL is usually 5 days.

3.What payment methods are accepted for AD9572ACPZPEC-RL?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9572ACPZPEC-RL transactions.

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4.How is shipping managed for AD9572ACPZPEC-RL?

AD9572ACPZPEC-RL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9572ACPZPEC-RL order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9572ACPZPEC-RL?

For technical support, including AD9572ACPZPEC-RL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9572ACPZPEC-RL requirements.

6.How does Aetrix verify that AD9572ACPZPEC-RL is sourced from the original manufacturer or authorized distributors?

All AD9572ACPZPEC-RL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9572ACPZPEC-RL meets industry standards.

7.What is the process for return or replacement of AD9572ACPZPEC-RL?

All AD9572ACPZPEC-RL units undergo pre-shipment inspection (PSI). If there is an issue with AD9572ACPZPEC-RL, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9572ACPZPEC-RL part is unused and in its original packaging.

Return procedure for AD9572ACPZPEC-RL:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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