Analog Devices Inc. AD9613-250EBZ

Overview

AD9613-250EBZ from Analog Devices is a high-speed evaluation board for the AD9613 12-bit, 250 MSPS analog-to-digital converter. It enables FPGA-based data capture via the HSC-ADC-EVALCZ interface, supports dual-channel analog inputs (J301/J303), accepts 10–14 dBm clock input at J506, and operates with 2.5 V FPGA I/O voltage configured via jumper J9.

For engineers reviewing the AD9613-250EBZ datasheet, AD9613-250EBZ pinout, AD9613-250EBZ application, or AD9613-250EBZ equivalent, this board provides validated signal integrity setup, SPI-controlled ADC configuration (via AD9613spiR03.cfg), DCO timing alignment (600 ps delay), and VisualAnalog/FFT-based performance validation for high-speed data acquisition systems.

Technical Context

The AD9613-250EBZ implements a complete test platform for the AD9613 IC, featuring dual 50 Ω SMA analog inputs (Channel A/B), a dedicated RF clock input (J506), and direct interconnect to the HSC-ADC-EVALCZ FPGA capture board via 120-pin mezzanine connector. It supports full-scale input signals of 8–12 dBm with external band-pass filtering.

Power delivery is split across two independent 6 V, 2 A switching supplies-one for the ADC board and one for the FPGA board-with jumper-selectable 2.5 V I/O voltage on the capture board. SPI communication uses the AD9613spiR03.cfg configuration file to initialize registers including FLEXOUTPUT DELAY(17) for DCO clock alignment.

Key Specifications

Availability

AD9613-250EBZ is available at Aetrix Electronics and suitable for high-speed data acquisition, radar receiver prototyping, and communications test equipment requiring stable component supply and repeatable ADC evaluation infrastructure.

Supply support for AD9613-250EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The AD9613-250EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, designed specifically to accelerate validation of RF-sampling data converters in defense, instrumentation, and broadband communications applications.

FAQ

What is the primary function of the AD9613-250EBZ?

The AD9613-250EBZ is an evaluation board built to characterize the AD9613 12-bit, 250 MSPS analog-to-digital converter. It provides calibrated analog input paths, precise clock injection, SPI register control, and FPGA-based data capture-enabling engineers to validate dynamic performance (SNR, SFDR, ENOB) and timing alignment before system integration. The AD9613-250EBZ requires the HSC-ADC-EVALCZ board for full functionality.

Does the AD9613-250EBZ include the AD9613 IC?

Yes, the AD9613-250EBZ evaluation board integrates the AD9613 12-bit, 250 MSPS ADC as its core device. The board is not a standalone module but a purpose-built platform for evaluating that specific IC under real-world signal conditions-including dual-channel analog input, programmable output timing, and SPI-configurable operating modes. The AD9613-250EBZ does not operate without the companion HSC-ADC-EVALCZ capture board.

What software tools are required to operate the AD9613-250EBZ?

Operation of the AD9613-250EBZ requires VisualAnalog for FFT-based performance analysis and SPIController for register-level configuration using the AD9613spiR03.cfg file. These tools enable DCO delay tuning, input formatting control, and FPGA programming of the HSC-ADC-EVALCZ. All software and documentation for the AD9613-250EBZ are hosted on analog.com/fifo.

How is clock signal integrity maintained on the AD9613-250EBZ?

The AD9613-250EBZ accepts a clean, low-phase-noise clock via SMA connector J506 at 10–14 dBm to drive the AD9613's sampling core. It supports internal clock division and includes DCO timing alignment controls (600 ps delay setting) to synchronize LVDS output edges with FPGA capture logic. Proper clock signal integrity is verified by observing FFT noise floor stability and absence of spurious tones during VisualAnalog testing of the AD9613-250EBZ.

Can the AD9613-250EBZ be used without the HSC-ADC-EVALCZ board?

No-the AD9613-250EBZ is not a self-contained evaluation system and cannot acquire or process data independently. It relies entirely on the HSC-ADC-EVALCZ FPGA-based capture board for LVDS data reception, FIFO buffering, USB streaming, and FPGA configuration. The AD9613-250EBZ connects to the HSC-ADC-EVALCZ via a 120-pin mezzanine interface, and both boards require separate 6 V, 2 A power supplies for operation.