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Analog Devices Inc. AD9613BCPZ-170
- Part No.:
- AD9613BCPZ-170
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad, CSP
- Datasheet:
-
AD9613BCPZ-170.pdf
- Description:
- IC ADC 12BIT PIPELINED 64LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:2,192
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Product details
Overview
AD9613BCPZ-170 from Analog Devices is a dual 12-bit, 170 MSPS analog-to-digital converter optimized for IF sampling in communications receivers. It features LVDS outputs, internal voltage reference, 1.8 V supply operation, and supports up to 400 MHz input frequencies with 95 dB channel isolation. It is used in TD-SCDMA and WiMAX baseband digitization where high dynamic range and low crosstalk are critical.
For engineers reviewing the AD9613BCPZ-170 datasheet, AD9613BCPZ-170 pinout, AD9613BCPZ-170 application, or AD9613BCPZ-170 equivalent, this page delivers verified specifications, validated pin functions, confirmed dual-channel timing behavior, and real-world deployment context for diversity radio and I/Q demodulation systems.
Technical Context
The AD9613BCPZ-170 implements two independent pipelined ADC cores with integrated error correction logic, each supporting differential analog inputs up to 400 MHz full-power bandwidth. Its duty cycle stabilizer (DCS) compensates for clock asymmetry, enabling stable performance at 170 MSPS without external clock conditioning.
Dual-channel data is output via parallel LVDS ports in either interleaved or channel-multiplexed format, synchronized using the dedicated SYNC input. Serial configuration uses a 3-wire SPI interface (CSB, SCLK, SDIO) with register readback capability and programmable power-down modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - delivers 72 dB theoretical SNR ceiling for precision IF sampling applications |
| Max Sample Rate | 170 MSPS - supports Nyquist-sampled LTE and W-CDMA carriers up to 85 MHz |
| SNR @ 90 MHz | 70.1 dBFS - enables >11-bit ENOB in 3G/4G receiver front ends with minimal noise floor degradation |
| SFDR @ 90 MHz | 92 dBc - suppresses spurious tones sufficiently for adjacent-channel rejection in multimode base stations |
| Input Bandwidth | 1000 MHz full-power bandwidth - preserves signal integrity for wideband IF inputs up to 400 MHz |
| Power Consumption | 738 mW at 170 MSPS - balances performance and thermal load in compact RF modules |
| Channel Isolation | 95 dB - prevents inter-channel leakage in smart antenna and MIMO receiver architectures |
Pinout & Package
The AD9613BCPZ-170 is housed in a 64-lead LFCSP (9 mm × 9 mm) package with exposed paddle requiring soldering to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK+, CLK− | Differential clock input | Accepts LVDS/CMOS/LVPECL clocks up to 625 MHz; DCS ensures jitter tolerance across duty cycle variation |
| VIN+A/VIN−A, VIN+B/VIN−B | Differential analog inputs (Ch A/B) | Support 1.4–2.0 Vp-p input range; 20 kΩ differential impedance and 2.5 pF capacitance define anti-alias filter design |
| D0+ to D11+, D0− to D11− | LVDS data outputs (12-bit per channel) | ANSI-644 compliant; 250–450 mV differential swing enables robust noise immunity on dense PCBs |
| DCO+, DCO− | Data clock output | LVDS-aligned clock for synchronous capture of output data; 0.4–1.0 ns skew tolerance simplifies FPGA interface timing |
| SYNC | Multi-device synchronization input | Enables deterministic phase alignment across multiple AD9613 units in phased-array or diversity receiver systems |
| CSB, SCLK, SDIO | SPI control interface | 3-wire serial port allows runtime register configuration including power modes, overrange thresholds, and output formatting |
Key Features
| Feature | Design Value |
|---|---|
| Integer 1-to-8 clock divider | Allows flexible system clock sourcing (e.g., 340 MHz master clock → 170 MSPS sample rate), reducing need for ultra-high-frequency oscillators |
| Internal voltage reference | Eliminates external reference IC and associated layout sensitivity, improving production yield and temperature stability |
| ADC clock duty cycle stabilizer (DCS) | Compensates for ±15% clock duty cycle variation, enabling use of low-cost crystal oscillators or PLLs without duty-cycle trimming |
| Fast overrange detection | OR+/OR− outputs flag saturation within 3 clock cycles, allowing immediate AGC adjustment in closed-loop receiver designs |
| Flexible power-down modes | Reduces power to 10 mW (full shutdown) or 90 mW (standby), supporting burst-mode operation in battery-powered test equipment |
Applications
| Communications Receiver | Smart Antenna System |
|---|---|
Use Scenario: Digitizing dual IF signals from separate antennas in a TD-SCDMA base station. IC Role / Device Role / Timing Role: Dual-channel ADC performing simultaneous sampling with <1 ps inter-channel jitter and 95 dB isolation. Use Value: Enables coherent beamforming by preserving phase relationship between channels while rejecting intermodulation from strong interferers. |
Use Scenario: Capturing spatially diverse RF paths in a 4×4 MIMO access point. IC Role / Device Role / Timing Role: Two synchronized ADCs providing time-aligned digital samples for real-time channel estimation algorithms. Use Value: Maintains sub-degree phase coherence across channels, directly supporting high-accuracy DOA estimation and adaptive nulling. |
| I/Q Demodulation Front End | Ultrasound Beamformer |
Use Scenario: Converting quadrature-mixed IF outputs in a software-defined radio transceiver. IC Role / Device Role / Timing Role: Channel A digitizes I-path, Channel B digitizes Q-path; interleaved LVDS output reduces FPGA pin count. Use Value: 70.1 dBFS SNR at 90 MHz preserves EVM in 64-QAM transmission chains; 1.8 V LVDS minimizes FPGA I/O power. |
Use Scenario: Sampling echo return signals from 128 transducer elements in portable ultrasound imaging. IC Role / Device Role / Timing Role: High-speed dual ADC capturing time-of-flight data with precise inter-channel timing alignment. Use Value: 1000 MHz full-power bandwidth supports wideband pulse-echo reception; low 0.39 LSBrms input noise improves contrast resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9643BCPZ-250 | 14-bit resolution, 250 MSPS max, same 64-lead LFCSP package and pinout | Higher ENOB (12.2 bits @ 90 MHz) but higher power (1.3 W); requires tighter layout for analog integrity | Select when >11-bit ENOB is required for narrowband LTE-A carrier aggregation or radar pulse analysis. |
| AD6649BCPZ | 14-bit, 250 MSPS, includes embedded digital down-converter (DDC) and JESD204B output | Reduces FPGA processing load via on-chip decimation; incompatible LVDS interface and larger 72-lead LFCSP | Choose when system-level bandwidth reduction and deterministic latency are prioritized over pin compatibility and analog flexibility. |
Compared with AD9613BCPZ-170, AD9643BCPZ-250 offers higher resolution at increased power and cost, while AD6649BCPZ shifts signal processing burden to the ADC but demands board redesign and new firmware integration.
Availability
AD9613BCPZ-170 is available at Aetrix Electronics and suitable for communications infrastructure, medical ultrasound, and defense electronics requiring stable component supply across multi-year production cycles.
Supply support for AD9613BCPZ-170 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The AD9613 belongs to Analog Devices' high-speed ADC product line, designed specifically for IF sampling in wireless infrastructure and instrumentation where dual-channel synchronization, low power, and wide input bandwidth are essential.
FAQ
What is the maximum analog input frequency supported by the AD9613BCPZ-170?
The AD9613BCPZ-170 has a full-power bandwidth of 1000 MHz, meaning it maintains specified AC performance (e.g., SNR, SFDR) for input signals up to 400 MHz. This enables direct IF sampling of cellular and WiMAX signals without image-reject filtering constraints typical of lower-bandwidth ADCs. The device's proprietary differential input architecture sustains 69.5 dBFS SNR even at 185 MHz input frequency.
Does the AD9613BCPZ-170 require an external voltage reference?
No, the AD9613BCPZ-170 integrates a precision internal voltage reference, eliminating the need for external reference components. This simplifies PCB layout, reduces bill-of-materials cost, and improves temperature stability-key for field-deployed communications equipment. The internal reference sets the 1.75 Vp-p nominal full-scale input range and remains stable across the −40°C to +85°C industrial temperature range.
How does the SYNC input function in multi-ADC synchronization with the AD9613BCPZ-170?
The SYNC input on the AD9613BCPZ-170 provides deterministic alignment of sampling edges across multiple devices. When asserted synchronously with the ADC clock, it resets internal pipeline stages to ensure sub-cycle phase coherence between AD9613BCPZ-170 units. This is essential for phased-array radar and MIMO systems where inter-channel timing error must remain below 10 ps to avoid beam distortion.
What LVDS output modes does the AD9613BCPZ-170 support?
The AD9613BCPZ-170 supports two LVDS output configurations: interleaved mode (single 12-bit bus carrying time-multiplexed Ch A/Ch B data) and channel-multiplexed (even/odd) mode (separate 12-bit buses for each channel). Mode selection is controlled via SPI register settings. Both modes comply with ANSI-644 levels, offering 250–450 mV differential swing and 1.15–1.35 V common-mode offset for reliable FPGA interfacing.
Can the AD9613BCPZ-170 operate with a 3.3 V digital supply?
No-the AD9613BCPZ-170 requires strictly 1.8 V supplies: AVDD (analog) and DRVDD (digital output driver). Applying 3.3 V to either supply violates Absolute Maximum Ratings and risks permanent damage. The device draws 241 mA from AVDD and 159 mA from DRVDD at 170 MSPS, totaling 738 mW. Power sequencing must follow AVDD before DRVDD, with both rails ramping monotonically.
AD9613BCPZ-170 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 170M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-LFCSP-VQ (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9613BCPZ-170 FAQ
1.How can I place an order for AD9613BCPZ-170 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9613BCPZ-170 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9613BCPZ-170 reliable?
The price and inventory of AD9613BCPZ-170 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9613BCPZ-170 is usually 5 days.
3.What payment methods are accepted for AD9613BCPZ-170?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9613BCPZ-170 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9613BCPZ-170?
AD9613BCPZ-170 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9613BCPZ-170 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9613BCPZ-170?
For technical support, including AD9613BCPZ-170 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9613BCPZ-170 requirements.
6.How does Aetrix verify that AD9613BCPZ-170 is sourced from the original manufacturer or authorized distributors?
All AD9613BCPZ-170 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9613BCPZ-170 meets industry standards.
7.What is the process for return or replacement of AD9613BCPZ-170?
All AD9613BCPZ-170 units undergo pre-shipment inspection (PSI). If there is an issue with AD9613BCPZ-170, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9613BCPZ-170 part is unused and in its original packaging.
Return procedure for AD9613BCPZ-170:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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