Analog Devices Inc. AD9625-2.6EBZ

Overview

AD9625-2.6EBZ from Analog Devices is a customer evaluation board designed to demonstrate the AD9625, a 12-bit, 2.6 GSPS analog-to-digital converter (ADC) with JESD204B serial interface, supporting high-speed data acquisition in radar, communications, and instrumentation systems.

For engineers reviewing the AD9625-2.6EBZ datasheet, AD9625-2.6EBZ pinout, AD9625-2.6EBZ application, or AD9625-2.6EBZ equivalent, this board provides full signal chain validation including clock distribution (via AD9525), SYSREF synchronization, FPGA interfacing, and configurable analog front-end options for differential input drive and common-mode voltage control.

Technical Context

The AD9625-2.6EBZ implements a complete reference design for the AD9625 ADC, featuring dual power domains (AVDD/DVDD/DRVDD at 1.2 V, 2.5 V, and 3.3 V), on-board LDOs (ADP1741, ADP7104, ADP2386), and precision decoupling networks across all supply rails. It supports both transformer-coupled and DC-coupled analog inputs via optional BAL0006SM balun or direct SMA connections.

JESD204B subclass 1 compliance is enabled through synchronized clocking (CLK±, SYSREF±, DSYNC±) and FPGA-configurable lane mapping. The board includes an AD9525 clock generator with six programmable outputs, enabling multi-device deterministic latency alignment critical for phased-array and MIMO applications.

Key Specifications

Availability

AD9625-2.6EBZ is available at Aetrix Electronics and suitable for high-speed data acquisition, phased-array radar prototyping, and 5G NR baseband development requiring stable component supply and validated reference designs.

Supply support for AD9625-2.6EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, defense, communications, and industrial markets since 1965.

The AD9625-2.6EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, engineered to accelerate time-to-validation for RF-sampling converters in demanding wideband applications such as electronic warfare and millimeter-wave test equipment.

FAQ

What is the primary function of the AD9625-2.6EBZ?

The AD9625-2.6EBZ is a customer evaluation board specifically built to evaluate the AD9625 12-bit, 2.6 GSPS analog-to-digital converter. It provides full hardware implementation-including clock generation (AD9525), power regulation, analog input conditioning, and JESD204B FPGA interface-to enable rapid system-level validation of high-speed sampling performance and timing alignment.

Does the AD9625-2.6EBZ support DC-coupled analog inputs?

Yes, the AD9625-2.6EBZ supports both AC-coupled (via BAL0006SM balun) and DC-coupled analog input configurations. The board includes jumpers and resistor networks (e.g., R301–R306) to configure VIN+/VIN− for direct differential DC coupling, with adjustable common-mode voltage (VCM) and biasing options per AD9625 datasheet requirements.

Which FPGA platforms is the AD9625-2.6EBZ compatible with?

The AD9625-2.6EBZ uses an ASP-134488-01 FMC-LPC connector compliant with ANSI/VITA 57.1, making it compatible with Xilinx Kintex-7, Virtex-7, and UltraScale-based carrier cards. Reference HDL and software drivers are provided by Analog Devices for Kintex-7 KC705 and VC707 platforms, ensuring plug-and-play integration with supported FPGA toolchains.

How is deterministic latency achieved on the AD9625-2.6EBZ?

Deterministic latency is achieved on the AD9625-2.6EBZ through strict JESD204B subclass 1 implementation: synchronized SYSREF distribution (FPGA_SYSREF_IN±), matched trace lengths for CLK±/DSYNC±/SYSREF±, and AD9525-generated clocks with phase-aligned outputs. This ensures repeatable, lockable lane alignment across power cycles and reconfigurations-critical for beamforming and TDD systems.

Can the AD9625-2.6EBZ operate without the AD9525 clock generator?

Yes-the AD9625-2.6EBZ supports external clock injection via SMA connectors (OPT_CLK_P/N). When bypassing the on-board AD9525, users must provide low-jitter differential clock (CLK±) and synchronized SYSREF± signals meeting AD9625's setup/hold and jitter specifications (<200 fs RMS typical). All required termination and AC-coupling components are pre-populated.