Analog Devices Inc. AD9625BBPZ-2.6
- Part No.:
- AD9625BBPZ-2.6
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 196-LFBGA Exposed Pad
- Datasheet:
-
AD9625BBPZ-2.6.pdf
- Description:
- IC ADC 12BIT PIPELINED 196BGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD9625BBPZ-2.6 from Analog Devices is a 12-bit, 2.6 GSPS monolithic analog-to-digital converter optimized for direct RF sampling in the second Nyquist zone. It features 3.2 GHz analog input bandwidth, −149.5 dBFS/Hz noise spectral density at 2.6 GSPS, and JESD204B subclass 1 serial output supporting 6.5 Gbps lane rate. It serves as the front-end digitizer in wideband radar receivers and electronic warfare systems.
For engineers reviewing the AD9625BBPZ-2.6 datasheet, AD9625BBPZ-2.6 pinout, AD9625BBPZ-2.6 application, or AD9625BBPZ-2.6 equivalent, key selection criteria include SFDR performance at 1.8 GHz (75.4 dBc), dual decimation filters with 10-bit NCOs, differential clock and SYSREF± inputs for multichip synchronization, and guaranteed no missing codes across industrial temperature range (−40°C to +85°C).
Technical Context
The AD9625BBPZ-2.6 implements a high-speed pipeline ADC architecture with integrated digital downconverters (DDCs) offering decimate-by-8 or decimate-by-16 filtering and numerically controlled oscillators (NCOs) for frequency translation. Its analog input stage supports 1.2 V p-p differential full-scale range and operates up to 3.2 GHz full-power bandwidth.
Digital output conforms to JESD204B subclass 1 with configurable 6- or 8-lane CML interface, enabling deterministic latency and multidevice synchronization via SYSREF±. Clock management includes aperture jitter of 80 fs rms and 226-cycle pipeline latency in eight-lane mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees monotonicity and no missing codes for accurate amplitude fidelity in wide dynamic range applications. |
| Max Sampling Rate | 2.6 GSPS - enables direct digitization of signals up to 1.3 GHz without analog downconversion. |
| SFDR @ 1.8 GHz | 75.4 dBc - ensures clean spectral representation for radar pulse detection and signal intelligence tasks. |
| SNR @ 1 GHz | 57.5 dBFS - delivers >9-bit effective resolution for high-fidelity waveform capture in spectrum analyzers. |
| Noise Density | −149.5 dBFS/Hz - minimizes quantization floor impact in narrowband receiver channelization. |
| Analog Bandwidth | 3.2 GHz - supports second Nyquist zone sampling of RF carriers up to L-band without external filtering. |
| JESD204B Lane Rate | 6.5 Gbps (6-lane) - reduces PCB routing complexity versus parallel CMOS while maintaining deterministic latency. |
| Power Dissipation | 4.3 W (eight-lane mode) - requires thermal management on 4-layer PCBs (θJA = 18.7°C/W) for sustained operation. |
Pinout & Package
AD9625BBPZ-2.6 is housed in a 144-lead LFCSP (12 mm × 12 mm × 1.2 mm, body), thermally enhanced with exposed paddle. Pin assignment follows a symmetric ground/power layout to suppress coupling between analog and digital domains.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+, VIN− | Differential analog input | Accepts 1.2 V p-p differential signal; 100 Ω input resistance and 1.5 pF capacitance require matched PCB trace design. |
| CLK+, CLK− | Differential sampling clock | Supports 330–2600 MSPS; 50% ±5% duty cycle required; 80 fs rms jitter tolerance defines system SNR limit. |
| SYSREF+, SYSREF− | Multi-device synchronization reference | Enables deterministic JESD204B link alignment; setup/hold times referenced to rising clock edge (tSU_SR = +200 ps, tH_SR = −100 ps). |
| SERDOUT[0]± to SERDOUT[7]± | JESD204B serial data outputs | CML-compliant; 360–800 mV p-p differential swing; 100 Ω differential termination required per lane. |
| RSTB | Asynchronous reset | Active-low; must be held low ≥2 clock cycles to initialize internal state machines and DDC registers. |
| SDIO, SCLK, CSB | Serial peripheral interface | CMOS-compatible SPI port for configuration of gain, offset, DDC modes, and test patterns; supports up to 25 MHz clock. |
Key Features
| Feature | Design Value |
|---|---|
| Dual DDC with 10-bit NCOs | Enables real-time frequency translation and channelization without FPGA resources-reduces system latency and processing load. |
| Timestamping via SYSREF± | Provides sub-cycle timing alignment across multiple AD9625BBPZ-2.6 devices for coherent beamforming in phased-array radar. |
| Flexible JESD204B lane count | Configurable 6- or 8-lane output allows trade-off between lane speed (6.5 Gbps vs. 5.2 Gbps) and PCB routing density. |
| Built-in digital test patterns | Includes PN23, ramp, and checkerboard sequences for production validation without external signal sources. |
| Conversion error rate | <10⁻¹⁵ - ensures bit-error-free operation over decades of continuous use in mission-critical defense electronics. |
| Differential clock and analog inputs | Rejects common-mode noise from high-speed digital switching, critical for mixed-signal integrity in compact radar modules. |
Applications
| Radar Receiver Front-End | Electronic Warfare Signal Intelligence |
|---|---|
Use Scenario: Digitizing pulsed L-band radar returns (1–2 GHz) with microsecond-level timing precision and high dynamic range. IC Role / Device Role / Timing Role: Primary ADC capturing raw IF or direct-RF samples; provides timestamped frames synchronized across multi-channel arrays. Use Value: 75.4 dBc SFDR at 1.8 GHz enables detection of weak targets masked by strong clutter; deterministic JESD204B subclass 1 latency supports real-time Doppler processing. |
Use Scenario: Wideband intercept of frequency-hopping communications and radar emissions across 100 MHz–2 GHz. IC Role / Device Role / Timing Role: High-speed digitizer feeding FPGA-based FFT and demodulation engines; uses DDC/NCO for instantaneous channel tuning. Use Value: 3.2 GHz analog bandwidth captures full instantaneous bandwidth; dual decimation filters allow simultaneous narrowband monitoring and wideband search. |
| Spectrum Analyzer Digitizer | Military Data Acquisition System |
Use Scenario: Real-time spectrum analysis in handheld or vehicle-mounted EW platforms requiring low-latency, high-resolution FFTs. IC Role / Device Role / Timing Role: Core sampling engine delivering 2.6 GSPS data to high-throughput memory buffers; leverages built-in test patterns for self-calibration. Use Value: −149.5 dBFS/Hz noise density preserves SNR in narrow RBW measurements; no missing codes ensures amplitude accuracy across full input range. |
Use Scenario: Recording high-fidelity sensor waveforms (e.g., acoustic, vibration, RF) in field-deployable test equipment for post-mission forensic analysis. IC Role / Device Role / Timing Role: Precision digitizer with timestamping and deterministic latency for time-correlated multi-sensor fusion. Use Value: Conversion error rate <10⁻¹⁵ guarantees data integrity over extended recording sessions; industrial temp range (−40°C to +85°C) ensures reliability in harsh environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCBZ-500 | 14-bit, 500 MSPS; lower sampling rate but higher ENOB (7.9 bits @ 1800 MHz vs. 8.9 bits for AD9625BBPZ-2.6) | Better suited for high-resolution narrowband applications (e.g., precision instrumentation), not wideband RF capture. | Select when SNR > SFDR is prioritized and 2.6 GSPS is unnecessary. |
| ADC12DJ3200IRSBT | 12-bit, dual-channel 3.2 GSPS; JESD204C support; higher power (5.3 W); 2.5 V supply only (no 1.3 V rail) | Enables time-interleaved sampling for wider instantaneous bandwidth; requires different power delivery and layout. | Choose for next-generation systems needing >2.6 GSPS or JESD204C migration path. |
Compared with AD9625BBPZ-2.6, AD9680BCBZ-500 trades raw speed for resolution in bandwidth-constrained scenarios, while ADC12DJ3200IRSBT extends sample rate and adds dual-channel capability at the cost of increased power and supply complexity-neither offers identical 2.6 GSPS + JESD204B subclass 1 + 3.2 GHz bandwidth combination.
Availability
AD9625BBPZ-2.6 is available at Aetrix Electronics and suitable for radar, electronic warfare, and high-performance test equipment requiring stable component supply, long-term obsolescence planning, and traceable sourcing for defense-grade programs.
Supply support for AD9625BBPZ-2.6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, defense, industrial, and communications markets since 1965.
The AD9625 product line delivers ultra-high-speed ADCs targeting direct RF sampling in defense electronics, where wide analog bandwidth, low jitter, and deterministic digital interfaces are mandatory for modern radar and SIGINT systems.
FAQ
What is the maximum analog input frequency supported by AD9625BBPZ-2.6?
The AD9625BBPZ-2.6 supports analog input frequencies up to 3.2 GHz full-power bandwidth, enabling direct sampling of signals in the second Nyquist zone (e.g., 1–2 GHz RF carriers). This specification is measured with internal termination and applies across the industrial temperature range (−40°C to +85°C).
Does AD9625BBPZ-2.6 support JESD204B subclass 1 synchronization?
Yes, AD9625BBPZ-2.6 fully supports JESD204B subclass 1, including deterministic latency and multidevice synchronization using SYSREF±. The device requires SYSREF± edges aligned to the rising clock edge with +200 ps setup and −100 ps hold time, enabling coherent operation in phased-array radar systems.
What power supplies are required for AD9625BBPZ-2.6 operation?
AD9625BBPZ-2.6 requires three independent voltage rails: AVDD1/DRVDD1/DVDD1 = 1.3 V (±30 mV), AVDD2/DRVDD2/DVDD2 = 2.5 V (±100 mV), and DVDDIO/SPI_VDDIO = 2.5 V or 3.3 V. Total power dissipation is 4.3 W in eight-lane mode at 2.6 GSPS, demanding careful thermal design on 4-layer PCBs.
Can AD9625BBPZ-2.6 perform digital downconversion internally?
Yes, AD9625BBPZ-2.6 integrates two independent digital downconverters (DDCs) with 10-bit numerically controlled oscillators (NCOs), supporting decimate-by-8 or decimate-by-16 filtering. This enables real-time frequency translation and channelization without external FPGA logic, reducing system latency and resource usage.
What is the conversion error rate specification for AD9625BBPZ-2.6?
The AD9625BBPZ-2.6 guarantees a conversion error rate of less than 10⁻¹⁵, meaning fewer than one erroneous sample per 10¹⁵ conversions. This ultra-low error rate ensures data integrity in mission-critical applications such as radar target tracking and electronic surveillance where undetected bit errors are unacceptable.
AD9625BBPZ-2.6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 196-LFBGA Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 2.6G
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- JESD204B
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 1.26V ~ 1.32V, 2.4V ~ 2.6V
- Voltage - Supply, Digital:
- 1.26V ~ 1.32V, 2.4V ~ 2.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 196-BGA-ED (12x12)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9625BBPZ-2.6 FAQ
1.How can I place an order for AD9625BBPZ-2.6 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9625BBPZ-2.6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9625BBPZ-2.6 reliable?
The price and inventory of AD9625BBPZ-2.6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9625BBPZ-2.6 is usually 5 days.
3.What payment methods are accepted for AD9625BBPZ-2.6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9625BBPZ-2.6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9625BBPZ-2.6?
AD9625BBPZ-2.6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9625BBPZ-2.6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9625BBPZ-2.6?
For technical support, including AD9625BBPZ-2.6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9625BBPZ-2.6 requirements.
6.How does Aetrix verify that AD9625BBPZ-2.6 is sourced from the original manufacturer or authorized distributors?
All AD9625BBPZ-2.6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9625BBPZ-2.6 meets industry standards.
7.What is the process for return or replacement of AD9625BBPZ-2.6?
All AD9625BBPZ-2.6 units undergo pre-shipment inspection (PSI). If there is an issue with AD9625BBPZ-2.6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9625BBPZ-2.6 part is unused and in its original packaging.
Return procedure for AD9625BBPZ-2.6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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