Analog Devices Inc. AD9626BCPZ-170

Overview

AD9626BCPZ-170 from Analog Devices is a 12-bit, 170 MSPS analog-to-digital converter optimized for wideband communications and radar subsystems. It features 64.4 dBFS SNR at 70 MHz input, ±0.6 LSB DNL, 700 MHz analog input bandwidth, and operates from a single 1.8 V supply. Its CMOS outputs support offset binary, twos complement, or Gray code formats for direct FPGA interfacing.

For engineers reviewing the AD9626BCPZ-170 datasheet, AD9626BCPZ-170 pinout, AD9626BCPZ-170 application, or AD9626BCPZ-170 equivalent, key selection considerations include sample rate headroom (170 MSPS), SNR/SFDR trade-offs at RF input frequencies up to 170 MHz, power dissipation of 272 mW in single-port mode, and compatibility with industrial temperature range (−40°C to +85°C) designs.

Technical Context

The AD9626BCPZ-170 employs a pipelined switched-capacitor ADC architecture with integrated track-and-hold, on-chip differential voltage reference, and digital error correction logic. Sampling occurs on the rising edge of the differential clock input, with aperture jitter of 0.2 ps rms and latency fixed at 6 clock cycles.

It supports two output configurations: single data port at up to 170 MHz or interleaved dual-port mode at 85 MHz per port. Clock duty cycle stabilization and programmable input voltage range (1.0–1.5 V p-p, nominal 1.25 V) enable flexible system-level timing and signal chain design without external decoupling.

Key Specifications

Pinout & Package

AD9626BCPZ-170 is housed in a 56-lead LFCSP (Lead Frame Chip Scale Package) with exposed paddle connected to AGND, specified for −40°C to +85°C operation. Thermal resistance θJA = 30.4°C/W (4-layer board, still air).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9625BCPZ-105, AD9626BCPZ-170 delivers +65 MSPS sample rate headroom and +10 dB SFDR at 70 MHz, justifying its use in modern broadband receivers; versus AD9680BCPZ-500, it offers lower power, smaller footprint, and simpler 1.8 V digital interface at the expense of resolution and maximum rate.

Availability

AD9626BCPZ-170 is available at Aetrix Electronics and suitable for wireless infrastructure, radar subsystems, and communications test equipment requiring stable component supply across extended product lifecycles.

Supply support for AD9626BCPZ-170 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and aerospace markets since 1965.

The AD9626 family was designed specifically for wideband carrier and broadband communication systems requiring high dynamic range, low power, and ease of FPGA interfacing - with AD9626BCPZ-170 targeting 170 MSPS applications in the industrial temperature range.

FAQ

What is the maximum analog input frequency supported by the AD9626BCPZ-170?

The AD9626BCPZ-170 has a full-power analog bandwidth of 700 MHz, meaning it can accurately digitize signals with fundamental components up to that frequency. However, usable input frequency depends on aliasing constraints and system-level filtering; for Nyquist-compliant sampling, the maximum baseband input is 85 MHz, though undersampling of higher-frequency IF signals (e.g., 140–170 MHz) is supported with appropriate anti-aliasing design.

Does the AD9626BCPZ-170 require external reference components?

No, the AD9626BCPZ-170 integrates a precision differential voltage reference and does not require external decoupling capacitors or reference ICs. The on-chip reference establishes a fixed 1.25 V p-p span for the 12-bit ADC core and is adjustable via SPI for fine calibration - simplifying PCB layout and reducing bill-of-materials cost.

Can the AD9626BCPZ-170 operate in interleaved dual-port mode at 170 MSPS?

No - in interleaved dual-port mode, the AD9626BCPZ-170 delivers two 85 MSPS data streams (one per port), maintaining aggregate throughput of 170 MSPS. Each port outputs half the samples, reducing per-lane timing requirements and enabling reliable capture on slower FPGA I/O standards without compromising overall sampling fidelity.

What digital output formats does the AD9626BCPZ-170 support?

The AD9626BCPZ-170 supports three programmable output data formats via SPI register control: offset binary (default), twos complement, and Gray code. This flexibility allows seamless integration with diverse FPGA logic families and DSP architectures - for example, Gray code minimizes metastability during clock domain crossing in high-speed designs.

How does the clock duty cycle stabilizer function in the AD9626BCPZ-170?

The AD9626BCPZ-170 includes an internal clock duty cycle stabilizer (DCS) that corrects asymmetry in the differential CLK+/CLK− input waveform. When enabled, it ensures near-50% duty cycle regardless of input skew or distortion, preserving sampling aperture accuracy and minimizing timing-dependent SNR degradation - especially critical when driven by integer-N PLLs or clock dividers.