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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. AD9627BCPZ-125

Name: AD9627BCPZ-125
Brand: Analog Devices Inc.
SKU: AD9627BCPZ-125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AD9627BCPZ-125

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 64-VFQFN Exposed Pad, CSP

Datasheet:: AD9627BCPZ-125.pdf

Description:: IC A/D 12BIT 125 MSPS DL 64LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AD9627BCPZ-125 from Analog Devices is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter with differential 650 MHz analog input bandwidth, 1.8 V analog supply operation, and CMOS or LVDS digital outputs. It features integrated sample-and-hold, internal voltage reference, clock duty cycle stabilizer, and fast detect/threshold monitoring for AGC in IF-sampling receivers.

For engineers reviewing the AD9627BCPZ-125 datasheet, AD9627BCPZ-125 pinout, AD9627BCPZ-125 application, or AD9627BCPZ-125 equivalent, this page delivers verified specifications, functional context, package mapping, and real-world deployment guidance for communications receiver design, diversity radio systems, and multimode baseband digitization.

Technical Context

The AD9627BCPZ-125 implements two independent pipelined ADC cores with multistage error correction logic, supporting simultaneous sampling at 125 MSPS with 69.4 dBc SNR and 85 dBc SFDR at 70 MHz input. Its differential analog inputs accept 1 V_p-p to 2 V_p-p ranges and maintain performance up to 450 MHz IF frequencies.

It integrates a serial port interface (SPI) for configuration of data formatting (offset binary/twos complement/gray), clock divider (1–8), power-down modes, and signal monitor functions. The device supports multichip synchronization via SYNC and DCO signals, and includes dedicated fast detect (FD0–FD3) and composite signal monitor blocks with low-latency serial output capability.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit - Enables precise digitization of wide dynamic range RF/IF signals in software-defined radios and base stations.
Sampling Rate	125 MSPS - Supports Nyquist-sampled IF signals up to 62.5 MHz or undersampled signals up to 450 MHz using bandpass sampling.
SNR @ 70 MHz	69.4 dBc - Delivers >11.4 ENOB for high-fidelity demodulation of WCDMA, LTE, and WiMAX waveforms.
Power Consumption	750 mW @ 125 MSPS - Optimized for thermally constrained small-cell and portable radio platforms with single 1.8 V AVDD supply.
Analog Input Bandwidth	650 MHz - Allows direct RF sampling of L-band and S-band signals without external amplification or filtering degradation.
Digital Output Interface	CMOS (1.8–3.3 V) or LVDS (1.8 V) - Ensures compatibility with FPGA I/O banks (e.g., Xilinx Kintex-7, Intel Arria 10) and reduces EMI in dense PCB layouts.
Channel Isolation	95 dB - Prevents crosstalk between dual channels in I/Q demodulation and smart antenna beamforming applications.

Pinout & Package

The AD9627BCPZ-125 is housed in a 64-lead, 9 mm × 9 mm, 0.8 mm pitch LFCSP (Lead Frame Chip Scale Package) with exposed thermal pad, rated for −40°C to +85°C industrial operation.

Pin/Terminal	Circuit Role	Design Meaning
VIN+A / VIN−A	Differential analog input, Channel A	Accepts balanced RF/IF signals up to 650 MHz; requires 50 Ω termination and AC coupling for optimal SNR.
VIN+B / VIN−B	Differential analog input, Channel B	Independent input path for I/Q or diversity signal acquisition; matched to Channel A within 0.2% gain and 0.3° phase.
CLK+ / CLK−	Differential clock input	Supports CMOS/LVDS/LVPECL; internal bias enables single-ended drive; DCS corrects duty cycle for jitter-sensitive sampling.
D0A–D11A / D0B–D11B	12-bit parallel digital outputs	CMOS or LVDS configurable; output drivers support 1.8 V or 3.3 V logic; timing-critical for FPGA capture at 125 MSPS.
DCOA / DCOB	Data clock output (LVDS)	Source-synchronous clock for Channel A/B data; enables deterministic FPGA timing closure without external clock routing.
SYNC	Multi-device synchronization input	Aligns sampling edges across multiple AD9627BCPZ-125 devices in phased-array or MIMO systems.
CSB / SCLK / SDIO	3-wire SPI interface	Configures register settings including gain control, test modes, data format, and signal monitor thresholds.
FD0–FD3A / FD0–FD3B	Fast detect magnitude bits	4-bit coarse amplitude indicator per channel with <10 ns latency-used for AGC loop response in <1 µs.

Key Features

Feature	Design Value
Dual independent ADC cores	Enables true I/Q sampling or spatial diversity reception without interleaving artifacts or timing skew compensation.
Integrated signal monitor block	Provides RMS, peak, or threshold-crossing detection on composite input with dedicated serial output-reduces FPGA resource load.
Programmable integer clock divider (1–8)	Allows flexible system clock architecture: e.g., 1 GHz input clock ÷ 8 = 125 MSPS sampling, easing clock generation and jitter management.
Internal 1.0 V reference with ±16 mV error	Eliminates external reference IC and associated layout sensitivity, reducing BOM count and improving temperature stability over −40°C to +85°C.
Low-power standby and power-down modes	Reduces current to 77 mW (standby) or 2.5–6 mW (power-down), enabling rapid wake-up (<350 µs) for burst-mode wireless protocols.

Applications

Communications Receiver	Diversity Radio System
Use Scenario: Digitizing dual-path IF signals in a 3G/4G base station transceiver with adaptive gain control. IC Role / Device Role / Timing Role: Dual-channel ADC performing simultaneous I/Q sampling at 125 MSPS with sub-10 ns fast detect latency for AGC feedback. Use Value: 95 dB channel isolation prevents inter-path interference; 69.4 dBc SNR ensures clean EVM for 64-QAM modulation under multipath conditions.	Use Scenario: Capturing spatially separated RF signals in a smart antenna array for beamforming and direction-of-arrival estimation. IC Role / Device Role / Timing Role: Two synchronized ADCs acquiring correlated signals with multichip SYNC alignment and matched pipeline latency (12/12.5 cycles). Use Value: Matched gain/phase response (<0.2% gain error, <0.3° phase error) enables coherent combining; 650 MHz bandwidth supports wide instantaneous bandwidth processing.
Multimode Digital Receiver	I/Q Demodulation System
Use Scenario: Supporting GSM, WCDMA, TD-SCDMA, and WiMAX standards in a single hardware platform via reconfigurable sampling and signal processing. IC Role / Device Role / Timing Role: Reconfigurable ADC core with SPI-controlled clock divider, data format, and signal monitor mode-enabling runtime adaptation to standard-specific IF frequencies and bandwidths. Use Value: Single 1.8 V AVDD simplifies power delivery; 125 MSPS rate covers all listed standards' maximum IF requirements (e.g., 30.72 MHz for LTE 20 MHz).	Use Scenario: Converting quadrature-mixed baseband signals from zero-IF or low-IF mixers into digital domain for FPGA-based demodulation. IC Role / Device Role / Timing Role: Dual ADC accepting differential I and Q inputs with matched DC offset and gain; outputs aligned via DCOA/DCOB clocks. Use Value: Integrated DC correction and 12-bit resolution preserve IQ balance critical for image rejection; 1.8 V LVDS outputs minimize noise coupling in mixed-signal PCBs.

Communications Receiver

Diversity Radio System

Use Scenario: Digitizing dual-path IF signals in a 3G/4G base station transceiver with adaptive gain control.

IC Role / Device Role / Timing Role: Dual-channel ADC performing simultaneous I/Q sampling at 125 MSPS with sub-10 ns fast detect latency for AGC feedback.

Use Value: 95 dB channel isolation prevents inter-path interference; 69.4 dBc SNR ensures clean EVM for 64-QAM modulation under multipath conditions.

Use Scenario: Capturing spatially separated RF signals in a smart antenna array for beamforming and direction-of-arrival estimation.

IC Role / Device Role / Timing Role: Two synchronized ADCs acquiring correlated signals with multichip SYNC alignment and matched pipeline latency (12/12.5 cycles).

Use Value: Matched gain/phase response (<0.2% gain error, <0.3° phase error) enables coherent combining; 650 MHz bandwidth supports wide instantaneous bandwidth processing.

Multimode Digital Receiver

I/Q Demodulation System

Use Scenario: Supporting GSM, WCDMA, TD-SCDMA, and WiMAX standards in a single hardware platform via reconfigurable sampling and signal processing.

IC Role / Device Role / Timing Role: Reconfigurable ADC core with SPI-controlled clock divider, data format, and signal monitor mode-enabling runtime adaptation to standard-specific IF frequencies and bandwidths.

Use Value: Single 1.8 V AVDD simplifies power delivery; 125 MSPS rate covers all listed standards' maximum IF requirements (e.g., 30.72 MHz for LTE 20 MHz).

Use Scenario: Converting quadrature-mixed baseband signals from zero-IF or low-IF mixers into digital domain for FPGA-based demodulation.

IC Role / Device Role / Timing Role: Dual ADC accepting differential I and Q inputs with matched DC offset and gain; outputs aligned via DCOA/DCOB clocks.

Use Value: Integrated DC correction and 12-bit resolution preserve IQ balance critical for image rejection; 1.8 V LVDS outputs minimize noise coupling in mixed-signal PCBs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9627BCPZ-105	Lower max sampling rate (105 MSPS); lower power (600 mW); identical pinout and feature set.	Suitable for cost-optimized receivers where 125 MSPS is not required-e.g., narrowband TD-SCDMA or legacy GSM.	Select when system IF bandwidth ≤ 52.5 MHz and thermal/power budget is tighter; no PCB change needed.
AD9640BCPZ-125	14-bit resolution, same 125 MSPS rate, identical 64-lead LFCSP package and pinout; higher SNR (73.5 dBc @ 70 MHz) but higher power (1.1 W).	Better suited for high-dynamic-range applications like radar pulse detection or wideband spectrum monitoring.	Choose for improved ENOB (>12 bits) and SFDR (>90 dBc) at expense of power and cost; drop-in replacement with firmware update.

Compared with AD9627BCPZ-105 and AD9640BCPZ-125, the AD9627BCPZ-125 uniquely balances 125 MSPS throughput, 12-bit precision, and 750 mW power in a compact LFCSP-making it optimal for space-constrained, mid-tier multimode receivers requiring both speed and efficiency.

Availability

AD9627BCPZ-125 is available at Aetrix Electronics and suitable for communications infrastructure, diversity radio systems, and multimode digital receivers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for AD9627BCPZ-125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, and aerospace markets since 1965.

The AD9627 product line targets high-speed data acquisition in wireless infrastructure, delivering dual-channel ADCs with integrated AGC assist features, low power, and flexible digital interfaces for rapid system integration.

FAQ

What is the maximum analog input frequency supported by the AD9627BCPZ-125?

The AD9627BCPZ-125 supports analog input frequencies up to 450 MHz using bandpass (undersampling) techniques, enabled by its 650 MHz analog input bandwidth and 125 MSPS sampling rate. At baseband, full-scale performance is maintained up to 70 MHz with 69.4 dBc SNR. Input drive must remain within the specified 1 V_p-p to 2 V_p-p differential range and comply with the 8 pF input capacitance and 6 kΩ VREF resistance limits defined in the AD9627BCPZ-125 datasheet.

Does the AD9627BCPZ-125 support LVDS output mode?

Yes, the AD9627BCPZ-125 supports LVDS output mode with a 1.8 V DRVDD supply, delivering differential output voltage (VOD) of 250–450 mV in ANSI mode or 150–280 mV in reduced-swing mode. LVDS operation requires proper termination (100 Ω differential) and is configured via SPI register settings. The device maintains 12-bit resolution and 125 MSPS throughput in LVDS mode, with DCOA/DCOB providing source-synchronous clocking for reliable FPGA capture.

How does the fast detect (FD) function operate in the AD9627BCPZ-125?

The AD9627BCPZ-125 provides four fast detect bits (FD0–FD3) per channel with <10 ns latency, indicating coarse input amplitude relative to programmable thresholds. These bits are updated every sample period and can trigger immediate AGC action-e.g., reducing mixer gain before an overrange event occurs. Thresholds are set via SPI registers, and FD outputs are available on dedicated pins or through the signal monitor serial port, enabling low-latency closed-loop control without FPGA intervention.

Is the AD9627BCPZ-125 pin-compatible with other members of the AD9627 family?

Yes, the AD9627BCPZ-125 shares identical 64-lead LFCSP packaging and pinout with AD9627BCPZ-80, AD9627BCPZ-105, and AD9627BCPZ-150. All variants use the same footprint, power supply connections, and digital interface signals. Performance differences (sampling rate, power, AC specs) are determined by internal configuration and process binning-not pin assignment-allowing hardware reuse across speed grades during design iteration or volume production scaling.

What power supply requirements must be met for reliable operation of the AD9627BCPZ-125?

The AD9627BCPZ-125 requires three independent supplies: AVDD = 1.8 V ±0.1 V (analog core), DVDD = 1.8 V ±0.1 V (digital core), and DRVDD = 1.8 V (LVDS) or 3.3 V (CMOS) for output drivers. Each supply must be decoupled with ≥10 µF bulk + 100 nF ceramic capacitors near the package. Total supply current is 385 mA (AVDD) + 42 mA (DVDD) + 36 mA (DRVDD = 3.3 V CMOS) at 125 MSPS, totaling ~750 mW. Ground planes must be solid and split only at the package thermal pad.

AD9627BCPZ-125 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad, CSP

Packaging:: Tray

Product Status:: Obsolete

Number of Bits:: 12

Sampling Rate (Per Second):: 125M

Number of Inputs:: -

Input Type:: -

Data Interface:: SPI

Configuration:: -

Ratio - S/H:ADC:: -

Number of A/D Converters:: 2

Architecture:: -

Reference Type:: -

Voltage - Supply, Analog:: -

Voltage - Supply, Digital:: -

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 64-LFCSP-VQ (9x9)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

AD9627BCPZ-125 FAQ

1.How can I place an order for AD9627BCPZ-125 through Aetrix?

Please submit a Request for Quotation (RFQ) for AD9627BCPZ-125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AD9627BCPZ-125 reliable?

The price and inventory of AD9627BCPZ-125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9627BCPZ-125 is usually 5 days.

3.What payment methods are accepted for AD9627BCPZ-125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9627BCPZ-125 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AD9627BCPZ-125?

AD9627BCPZ-125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AD9627BCPZ-125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AD9627BCPZ-125?

For technical support, including AD9627BCPZ-125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9627BCPZ-125 requirements.

6.How does Aetrix verify that AD9627BCPZ-125 is sourced from the original manufacturer or authorized distributors?

All AD9627BCPZ-125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9627BCPZ-125 meets industry standards.

7.What is the process for return or replacement of AD9627BCPZ-125?

All AD9627BCPZ-125 units undergo pre-shipment inspection (PSI). If there is an issue with AD9627BCPZ-125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AD9627BCPZ-125 part is unused and in its original packaging.

Return procedure for AD9627BCPZ-125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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