Analog Devices Inc. AD9628BCPZ-105

Overview

AD9628BCPZ-105 from Analog Devices is a dual-channel, 12-bit, 105 MSPS analog-to-digital converter operating from a single 1.8 V analog supply, featuring differential analog inputs (650 MHz bandwidth), on-chip voltage reference, and 1.8 V CMOS or LVDS digital outputs. It delivers 71.3 dBFS SNR and 93 dBc SFDR at 70 MHz input, supporting IF sampling up to 200 MHz in communications receivers and ultrasound systems.

For engineers reviewing the AD9628BCPZ-105 datasheet, AD9628BCPZ-105 pinout, AD9628BCPZ-105 application, or AD9628BCPZ-105 equivalent, this page provides verified technical context, real-world timing behavior, package-specific layout guidance, and validated alternative options for diversity radio, I/Q demodulation, and portable medical imaging designs.

Technical Context

The AD9628BCPZ-105 implements a multistage differential pipeline architecture with output error correction logic, guaranteeing no missing codes over −40°C to +85°C. Its patented sample-and-hold circuit supports full-scale sine-wave inputs up to 200 MHz while maintaining 71.2 dBFS SNR and ±0.25 LSB DNL at 25°C.

It integrates a programmable integer 1-to-8 clock divider, optional duty cycle stabilizer (DCS), and serial port interface (SPI) for configuring data format (offset binary/Gray/twos complement), clock/data alignment, and built-in test patterns. Dual-channel synchronization is supported via SYNC pin with 0.24 ns setup and 0.40 ns hold timing.

Key Specifications

Pinout & Package

The AD9628BCPZ-105 is housed in a 64-lead RoHS-compliant LFCSP (9 mm × 9 mm) with exposed thermal pad requiring solder connection to PCB ground plane for proper thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit ADC applications.

Compared with AD9628BCPZ-125, the AD9628BCPZ-105 reduces power by 28 mW at same temperature and supply conditions while retaining identical noise, linearity, and interface features; versus AD9231BCPZ-105, it adds deterministic dual-channel latency alignment and independent output clocks-critical for I/Q and MIMO systems.

Availability

AD9628BCPZ-105 is available at Aetrix Electronics and suitable for communications receivers, portable medical imaging, and battery-powered test equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for AD9628BCPZ-105 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and a 50+ year heritage in precision data conversion.

The AD9628 product line targets high-speed, low-power, dual-channel digitization for wireless infrastructure, defense electronics, and portable instrumentation-designed to replace discrete ADC + FPGA solutions with integrated timing, reference, and interface functions.

FAQ

What is the maximum analog input frequency supported by the AD9628BCPZ-105?

The AD9628BCPZ-105 supports analog input frequencies up to 200 MHz while maintaining specified SNR and SFDR performance. This is enabled by its 650 MHz small-signal analog input bandwidth and optimized sample-and-hold circuit, making it suitable for intermediate frequency (IF) sampling in communications and radar applications. The AD9628BCPZ-105 achieves 69.4 dBFS SNR at 200 MHz input, confirming usable bandwidth beyond the Nyquist limit of its 105 MSPS sampling rate.

Does the AD9628BCPZ-105 require an external voltage reference?

No, the AD9628BCPZ-105 includes an on-chip 1.0 V voltage reference with ±2 mV load regulation error at 1.0 mA, eliminating the need for an external reference in most applications. The VREF pin can be used as input or output, and SENSE selects internal or external reference mode. When using the internal reference, the AD9628BCPZ-105 delivers guaranteed 12-bit performance across temperature without calibration.

How does the SYNC pin function in the AD9628BCPZ-105?

The SYNC pin on the AD9628BCPZ-105 provides deterministic channel-to-channel synchronization for dual-channel operation. When asserted, it aligns the internal pipeline states of Channel A and Channel B to ensure identical latency and phase response-critical for I/Q demodulation and beamforming. Timing requirements specify 0.24 ns setup and 0.40 ns hold relative to CLK+, enabling precise multi-device coherence in synchronized ADC arrays.

What are the power consumption differences between CMOS and LVDS output modes for the AD9628BCPZ-105?

In CMOS mode (DRVDD = 1.8 V), the AD9628BCPZ-105 consumes 173 mW with a sine-wave input; in LVDS mode, it consumes 243 mW under identical conditions. The 70 mW difference arises from LVDS's differential current-mode drivers. CMOS mode is preferred for ultra-low-power portable systems, while LVDS provides superior noise immunity and timing margin for high-speed FPGA interfaces-both supported without changing the AD9628BCPZ-105 hardware.

Is the AD9628BCPZ-105 pin-compatible with other Analog Devices ADCs?

Yes, the AD9628BCPZ-105 uses a 64-lead LFCSP package pin-compatible with the AD9650/AD9269/AD9268 (16-bit), AD9258/AD9251/AD9648 (14-bit), AD9231 (12-bit), and AD9608/AD9204 (10-bit) families. This enables seamless migration across resolution and speed grades-from 20 MSPS to 125 MSPS-while preserving PCB layout, power delivery, and thermal design across generations of Analog Devices high-speed ADCs.