Analog Devices Inc. AD9628BCPZ-125

Overview

AD9628BCPZ-125 from Analog Devices is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter operating from a single 1.8 V analog supply, featuring differential analog inputs with 650 MHz bandwidth, SNR of 71.2 dBFS at 70 MHz, and on-chip voltage reference-used in I/Q demodulation systems for LTE and W-CDMA baseband receivers.

For engineers reviewing the AD9628BCPZ-125 datasheet, AD9628BCPZ-125 pinout, AD9628BCPZ-125 application, or AD9628BCPZ-125 equivalent, key selection criteria include dual-channel interleaving support, LVDS/CMOS output flexibility, programmable clock divider (1-to-8), deterministic test pattern generation, and industrial temperature range (−40°C to +85°C) operation.

Technical Context

The AD9628BCPZ-125 employs a multistage differential pipeline architecture with output error correction logic to guarantee 12-bit accuracy and no missing codes across temperature. It supports IF sampling up to 200 MHz and includes an optional duty cycle stabilizer to maintain performance under wide clock duty cycle variation.

Its dual ADC cores share a common clock input but operate independently, enabling synchronized sampling with programmable channel alignment via DCO timing control. The device integrates a 1.0 V internal reference, sample-and-hold circuit, and configurable digital output formatting (offset binary, Gray, or twos complement).

Key Specifications

Pinout & Package

The AD9628BCPZ-125 is housed in a 64-lead RoHS-compliant LFCSP (9 mm × 9 mm) with exposed thermal pad requiring solder connection to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit ADC applications.

Compared with AD9628BCPZ-125, AD9627BCPZ-105 offers lower power and cost at reduced speed, while AD9231BCPZ-125 sacrifices channel correlation and system integration for simpler layout and lower component count in single-path architectures.

Availability

AD9628BCPZ-125 is available at Aetrix Electronics and suitable for communications infrastructure, portable medical imaging, and radar signal acquisition requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for AD9628BCPZ-125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets since 1965.

The AD9628 product line delivers high-speed, low-power dual-channel ADCs optimized for software-defined radio, wireless infrastructure, and real-time signal intelligence applications demanding precision, synchronization, and flexible digital interfacing.

FAQ

What is the maximum analog input frequency supported by the AD9628BCPZ-125?

The AD9628BCPZ-125 supports IF sampling frequencies up to 200 MHz with maintained AC performance, enabled by its 650 MHz analog input bandwidth and patented sample-and-hold circuit. At 200 MHz input, SNR remains at 69.4 dBFS and SFDR at 83 dBc, making it suitable for direct undersampling of L-band and S-band signals without external pre-filtering.

Does the AD9628BCPZ-125 support both CMOS and LVDS digital outputs simultaneously?

No-the AD9628BCPZ-125 supports either 1.8 V CMOS or LVDS output logic levels, selected at power-up via the REF SELECT pin and SPI configuration. Both output types share the same D0A–D11A/D0B–D11B pins and cannot be active concurrently; the choice affects DRVDD rail requirements and FPGA I/O bank configuration.

How is channel synchronization achieved between the two ADCs in the AD9628BCPZ-125?

Channel synchronization in the AD9628BCPZ-125 is achieved through a shared differential clock input (CLK+/CLK−) and optional SYNC pin assertion, which aligns internal sampling phases across both channels. The device guarantees inter-channel offset error <±0.01% FSR and gain error <±1.0% FSR, ensuring coherent I/Q demodulation without post-processing calibration.

What is the purpose of the RBIAS pin on the AD9628BCPZ-125?

The RBIAS pin on the AD9628BCPZ-125 connects to a 10 kΩ (1%) resistor to AGND to set the bias current for the internal voltage reference and sample-and-hold circuitry. This external resistor ensures stable reference voltage (1.0 V ±2%) and optimal DNL performance; omission or incorrect value degrades SNR and introduces gain drift.

Can the AD9628BCPZ-125 operate without an external clock source?

No-the AD9628BCPZ-125 requires an external differential clock applied to CLK+/CLK− pins for all conversion operations. It does not include an on-chip oscillator or PLL clock generator. However, the optional duty cycle stabilizer (DCS) function compensates for input clock duty cycle variations from 30% to 70%, preserving aperture jitter below 0.137 ps rms.