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Analog Devices Inc. AD9628BCPZRL7-125
- Part No.:
- AD9628BCPZRL7-125
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad, CSP
- Datasheet:
-
AD9628BCPZRL7-125.pdf
- Description:
- IC ADC 12BIT PIPELINED 64LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,227
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Product details
Overview
AD9628BCPZRL7-125 from Analog Devices is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter operating from a single 1.8 V analog supply, featuring differential analog inputs with 650 MHz bandwidth, SNR of 71.2 dBFS at 70 MHz, and LVDS/CMOS output compatibility - deployed in IF-sampling receivers for LTE and radar systems.
For engineers reviewing the AD9628BCPZRL7-125 datasheet, AD9628BCPZRL7-125 pinout, AD9628BCPZRL7-125 application, or AD9628BCPZRL7-125 equivalent, key selection considerations include sampling rate (125 MSPS), dual-channel synchronization capability, on-chip voltage reference, programmable clock divider (1-to-8), and support for deterministic digital test pattern generation.
Technical Context
The AD9628BCPZRL7-125 employs a multistage differential pipeline architecture with error correction logic to guarantee 12-bit accuracy and no missing codes across −40°C to +85°C. It integrates a patented sample-and-hold circuit optimized for IF sampling up to 200 MHz and supports both CMOS and LVDS digital outputs via separate DRVDD supply.
Its serial port interface enables configuration of data format (offset binary/Gray/twos complement), duty cycle stabilizer activation, DCO/data alignment, and channel-specific power-down modes. The ADC accepts differential clock inputs compliant with CMOS/LVDS/LVPECL standards and includes built-in crosstalk isolation (−95 dB) between channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - guarantees monotonicity and no missing codes over full industrial temperature range. |
| Sampling Rate | 125 MSPS - maximum conversion rate with DCS enabled; supports real-time digitization of wideband IF signals. |
| SNR @ 70 MHz | 71.2 dBFS - defines dynamic range limit for high-fidelity signal capture in communications receivers. |
| Input Bandwidth | 650 MHz - enables direct RF sampling of L-band and S-band signals without external amplification. |
| Power Consumption | 101 mW/channel @ 125 MSPS - low-power operation suitable for battery-powered portable ultrasound and handheld test equipment. |
| Differential Nonlinearity | ±0.25 LSB (25°C) - ensures precise amplitude fidelity critical for I/Q demodulation accuracy. |
| Analog Input Span | 2 V p-p differential - matches standard transformer-coupled or balun-based front-end designs. |
| Latency (LVDS) | 16/16.5 cycles - deterministic pipeline delay enabling synchronized multi-ADC timing in phased-array radar. |
Pinout & Package
The AD9628BCPZRL7-125 is housed in a 64-lead RoHS-compliant LFCSP (9 mm × 9 mm) with exposed thermal pad requiring soldering to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+A / VIN−A | Differential analog input (Channel A) | Accepts 2 V p-p differential signal; common-mode bias set by internal VCM (0.9 V) or external source. |
| VIN+B / VIN−B | Differential analog input (Channel B) | Independent second channel with matched gain/offset tracking for diversity or I/Q sampling. |
| CLK+ / CLK− | Differential clock input | Controls all internal conversions; supports CMOS/LVDS/LVPECL; optional duty cycle stabilizer improves jitter tolerance. |
| D0A–D11A / D0B–D11B | Parallel digital outputs | 12-bit CMOS or LVDS data per channel; MSB/LSB labeling enables correct bus routing in FPGA interfaces. |
| DCOA / DCOB | Data clock output | Source-synchronous clock aligned to output data; programmable phase offset supports timing closure in high-speed logic. |
| AVDD (Pins 49,50,53,54,59,60,63,64) | Analog power supply | Single 1.8 V rail powers core ADC and reference; requires local decoupling near each pin per layout guidelines. |
| DRVDD (Pins 10,19,28,37) | Digital output driver supply | Separate 1.8 V rail isolates digital switching noise from analog section; enables mixed-voltage system interfacing. |
| SYNC | Synchronization input | Enables deterministic multi-device alignment; required for time-coherent sampling across multiple AD9628 units. |
| OEB | Output enable (active low) | Tri-states all digital outputs; used for shared-bus arbitration or power sequencing control. |
| PDWN | Power-down input | Reduces power to 2.0 mW; wake-up time is 350 µs - suitable for burst-mode acquisition in radar pulse processing. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip voltage reference | 1.0 V ±2% output with 2 mV load regulation - eliminates need for external precision reference in space-constrained designs. |
| Programmable clock divider | Integer 1-to-8 division - allows use of lower-frequency, lower-jitter master clocks while maintaining target sampling rate. |
| Built-in test pattern generation | Deterministic, pseudorandom, and user-defined patterns accessible via SPI - accelerates board-level validation without external signal sources. |
| Data output multiplex option | Interleaved or channel-multiplexed mode - reduces FPGA pin count by 50% when bandwidth permits time-division sharing. |
| Offset binary / Gray / twos complement formatting | Software-selectable via SPI register - simplifies integration with DSP cores requiring specific data encoding conventions. |
| Channel synchronization | Hardware SYNC input with sub-nanosecond setup/hold timing - enables coherent sampling across multiple AD9628 devices in MIMO or beamforming arrays. |
Applications
| Communications Receiver | Radar Signal Processing |
|---|---|
|
Use Scenario: Dual-channel digitization of I/Q baseband signals in multimode cellular base stations supporting LTE and W-CDMA. IC Role / Device Role / Timing Role: Simultaneous sampling of in-phase and quadrature analog paths with matched gain, offset, and latency. Use Value: Enables direct-conversion receiver architectures with <−85 dBc SFDR at 70 MHz, meeting 3GPP ACLR requirements. |
Use Scenario: High-speed digitization of pulsed Doppler returns in X-band phased-array radar systems. IC Role / Device Role / Timing Role: Time-aligned dual-channel capture of echo signals across antenna elements for beamforming computation. Use Value: 125 MSPS rate and 650 MHz input bandwidth support 100 MHz instantaneous bandwidth needed for range resolution ≤1.5 m. |
| Portable Ultrasound Imaging | Smart Antenna Test Equipment |
|
Use Scenario: Compact beamformer module in handheld ultrasound scanners requiring low power and high SNR. IC Role / Device Role / Timing Role: Digitizing RF echoes from piezoelectric transducers with minimal added noise floor. Use Value: 71.2 dBFS SNR at 70 MHz preserves tissue contrast resolution; 101 mW/channel extends battery life in Class I medical devices. |
Use Scenario: Real-time analysis of spatially diverse RF signals in 5G NR massive MIMO OTA testing setups. IC Role / Device Role / Timing Role: Synchronized sampling across multiple RF front-ends to characterize antenna correlation and radiation patterns. Use Value: −95 dB inter-channel crosstalk ensures measurement integrity; SYNC pin enables sub-cycle alignment across 8+ ADC channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 12-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9627BCPZRL7-105 | Lower sampling rate (105 MSPS); identical pinout, package, and feature set except clock divider max = 1:4. | Targeted at cost-sensitive IF sampling where 105 MSPS suffices (e.g., legacy GSM/WiMAX). | Select when system clock constraints or power budget favor reduced throughput without sacrificing interface compatibility. |
| AD9680BCPZRL7-500 | Higher resolution (14-bit), higher speed (500 MSPS), larger 72-lead LFCSP package; not pin-compatible. | Used in wideband electronic warfare and high-definition imaging where ENOB >11.5 bits is mandatory. | Choose only if SNR/SFDR requirements exceed AD9628BCPZRL7-125 capabilities; expect PCB redesign and firmware adaptation. |
Compared with AD9628BCPZRL7-125, AD9627BCPZRL7-105 offers identical functionality at lower speed and power, while AD9680BCPZRL7-500 delivers superior dynamic performance but demands new layout, thermal management, and digital interface design.
Availability
AD9628BCPZRL7-125 is available at Aetrix Electronics and suitable for communications infrastructure, radar signal acquisition, and portable medical imaging requiring stable component supply and long-term production continuity.
Supply support for AD9628BCPZRL7-125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with R&D centers worldwide.
The AD9628BCPZRL7-125 belongs to Analog Devices' high-speed data converter product line, engineered specifically for demanding IF-sampling applications in wireless infrastructure, defense electronics, and medical imaging systems.
FAQ
What is the maximum analog input frequency supported by the AD9628BCPZRL7-125?
The AD9628BCPZRL7-125 supports analog input frequencies up to 200 MHz in IF sampling mode, enabled by its 650 MHz analog input bandwidth and patented sample-and-hold circuit. This allows direct digitization of L-band and S-band signals without downconversion, as verified in the "Analog Input Considerations" section of the Rev. C datasheet.
Does the AD9628BCPZRL7-125 support both CMOS and LVDS output formats simultaneously?
No, the AD9628BCPZRL7-125 supports either CMOS or LVDS output logic levels-not both simultaneously-selected via configuration registers and DRVDD voltage level. When DRVDD = 1.8 V, LVDS mode requires external termination; CMOS mode drives standard 1.8 V logic directly, as specified in Table 3 of the AD9628 Rev. C datasheet.
How is channel synchronization achieved across multiple AD9628BCPZRL7-125 devices?
Channel synchronization across multiple AD9628BCPZRL7-125 units is achieved using the dedicated SYNC input pin, which aligns internal sampling phases with sub-nanosecond timing precision. The device requires a common clock and synchronized SYNC pulses, as detailed in the "Channel/Chip Synchronization" section (Page 30) of the Rev. C datasheet.
What is the purpose of the RBIAS pin on the AD9628BCPZRL7-125?
The RBIAS pin on the AD9628BCPZRL7-125 connects to a 10 kΩ (1%) resistor to AGND to set the internal bias current for the on-chip voltage reference and sample-and-hold circuit. This external resistor ensures stable reference voltage (1.0 V) and optimal SNR performance, as defined in Table 8 and Figure 24 of the Rev. C datasheet.
Can the AD9628BCPZRL7-125 operate with an external voltage reference?
Yes, the AD9628BCPZRL7-125 can operate with an external voltage reference applied to the VREF pin, bypassing the internal 1.0 V reference. The SENSE pin must be tied appropriately to select external mode, and the reference must meet noise and stability requirements outlined in the "Voltage Reference" section (Page 27) of the Rev. C datasheet.
AD9628BCPZRL7-125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 125M
- Number of Inputs:
- 2
- Input Type:
- Differential, Single Ended
- Data Interface:
- LVDS - Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-LFCSP-VQ (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9628BCPZRL7-125 FAQ
1.How can I place an order for AD9628BCPZRL7-125 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9628BCPZRL7-125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9628BCPZRL7-125 reliable?
The price and inventory of AD9628BCPZRL7-125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9628BCPZRL7-125 is usually 5 days.
3.What payment methods are accepted for AD9628BCPZRL7-125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9628BCPZRL7-125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9628BCPZRL7-125?
AD9628BCPZRL7-125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9628BCPZRL7-125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9628BCPZRL7-125?
For technical support, including AD9628BCPZRL7-125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9628BCPZRL7-125 requirements.
6.How does Aetrix verify that AD9628BCPZRL7-125 is sourced from the original manufacturer or authorized distributors?
All AD9628BCPZRL7-125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9628BCPZRL7-125 meets industry standards.
7.What is the process for return or replacement of AD9628BCPZRL7-125?
All AD9628BCPZRL7-125 units undergo pre-shipment inspection (PSI). If there is an issue with AD9628BCPZRL7-125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9628BCPZRL7-125 part is unused and in its original packaging.
Return procedure for AD9628BCPZRL7-125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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