Analog Devices Inc. AD9629BCPZ-80

Overview

AD9629BCPZ-80 from Analog Devices is a 12-bit, 80 MSPS monolithic analog-to-digital converter operating from a single 1.8 V analog supply, featuring differential 700 MHz input bandwidth, on-chip voltage reference and sample-and-hold, and CMOS/LVDS/LVPECL clock compatibility - deployed in LTE baseband receivers and portable ultrasound front-ends.

For engineers reviewing the AD9629BCPZ-80 datasheet, AD9629BCPZ-80 pinout, AD9629BCPZ-80 application, or AD9629BCPZ-80 equivalent, key selection criteria include SNR (71.3 dBFS at 9.7 MHz), SFDR (95 dBc at 9.7 MHz), DNL (±0.16 LSB), 32-lead LFCSP package with exposed paddle grounding, and programmable clock/data alignment via SPI.

Technical Context

The AD9629BCPZ-80 implements a multistage differential pipeline architecture with output error correction logic to guarantee 12-bit accuracy and no missing codes across −40°C to +85°C. It supports integer clock division by 1, 2, or 4 and accepts differential clock inputs up to 320 MHz (pre-divider).

Its analog input stage delivers 700 MHz small-signal bandwidth with 2 V p-p differential full-scale range and 0.9 V common-mode voltage; digital outputs operate at 1.8 V to 3.3 V logic levels with programmable data format (offset binary, gray, twos complement) and built-in deterministic/pseudorandom test pattern generation.

Key Specifications

Pinout & Package

The AD9629BCPZ-80 is housed in a 32-lead, 5 mm × 5 mm RoHS-compliant LFCSP with exposed paddle (EPAD), requiring soldering to AGND for thermal management, noise reduction, and mechanical reliability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9629BCPZ-80, AD9609BCPZ-80 trades 2 bits of resolution for lower cost and power, while AD9649BCPZ-80 adds 2 bits at higher power and price - all three share identical footprint, timing, and control architecture for seamless scalability.

Availability

AD9629BCPZ-80 is available at Aetrix Electronics and suitable for LTE infrastructure, portable medical imaging, and automotive radar requiring stable component supply with guaranteed long-term availability and traceable sourcing.

Supply support for AD9629BCPZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The AD9629 belongs to Analog Devices' high-speed ADC product line, engineered for communications, medical imaging, and instrumentation applications demanding precision, low power, and robust RF performance in compact packages.

FAQ

What is the maximum analog input frequency supported by the AD9629BCPZ-80?

The AD9629BCPZ-80 features a 700 MHz small-signal analog input bandwidth, enabling digitization of signals up to 200 MHz while maintaining 69.0 dBFS SNR. This supports undersampling architectures for UHF radio and radar applications without external bandpass filtering.

Does the AD9629BCPZ-80 require external reference components?

No - the AD9629BCPZ-80 integrates a precision 1.0 V voltage reference and sample-and-hold circuit. External components are only needed if using an external reference: connect VREF to a stable 1.0 V source and set SENSE accordingly per Table 10 of the datasheet.

How is the exposed paddle (EPAD) of the AD9629BCPZ-80 grounded?

The exposed paddle (Pin 0) is the sole ground connection for the AD9629BCPZ-80 and must be soldered directly to the analog ground (AGND) plane of the PCB. Failure to do so compromises thermal dissipation, noise performance, and mechanical reliability.

Can the AD9629BCPZ-80 operate with a 3.3 V digital interface?

Yes - the AD9629BCPZ-80 supports 1.8 V to 3.3 V digital output levels via the DRVDD supply pin. When DRVDD = 3.3 V, D0–D11 and DCO outputs meet 3.3 V CMOS voltage thresholds with 3.25 V VOH (at 0.5 mA) and 0.2 V VOL (at 1.6 mA).

What clock input standards does the AD9629BCPZ-80 support?

The AD9629BCPZ-80 accepts differential clock inputs compliant with CMOS, LVDS, or LVPECL standards. The internal common-mode bias is fixed at 0.9 V, and differential input voltage range spans 0.2 V to 3.6 V p-p - accommodating diverse clock generator outputs.