Analog Devices Inc. AD9633BCPZ-80
- Part No.:
- AD9633BCPZ-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-WFQFN Exposed Pad, CSP
- Datasheet:
-
AD9633BCPZ-80.pdf
- Description:
- IC ADC 12BIT PIPELINED 48LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AD9633BCPZ-80 from Analog Devices is a quad-channel, 12-bit, 80 MSPS analog-to-digital converter with serial LVDS output, 1.8 V supply operation, 71 dB SNR (to Nyquist), and 650 MHz full-power analog bandwidth-designed for medical ultrasound front-ends requiring high channel density and low power per channel.
For engineers reviewing the AD9633BCPZ-80 datasheet, AD9633BCPZ-80 pinout, AD9633BCPZ-80 application, or AD9633BCPZ-80 equivalent, this page delivers verified specifications, validated pin functions, confirmed industrial-temperature operation (−40°C to +85°C), and real-world use context for high-speed imaging and quadrature radio receiver signal chains.
Technical Context
The AD9633BCPZ-80 implements a multistage pipelined ADC architecture with 1-bit redundancy per stage for digital error correction, sampling on the rising edge of the clock and delivering aligned 12-bit DDR LVDS data across two lanes. It integrates a 1.0 V internal reference, programmable output clock/data alignment, and multichip sync support via the SYNC input.
It supports dual LVDS output modes-ANSI-644 compliant (345 mV typical VOD) and low-power reduced-signal mode (200 mV typical VOD)-with configurable resolution (10/12-bit), frame rate (1×/2×), and lane count (one/two). Digital control is implemented via a 3-wire SPI interface (SCLK, SDIO, CSB) with memory-mapped register access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit-enables precise digitization of wide dynamic range signals in ultrasound beamforming and RF I/Q processing. |
| Sample Rate | 80 MSPS-supports baseband and IF sampling up to 70 MHz input frequency while maintaining ≥70 dB SNR. |
| SNR (to Nyquist) | 71.7 dBFS at 9.7 MHz input-ensures high-fidelity signal capture for diagnostic-grade medical imaging. |
| SFDR | 96 dBc at 9.7 MHz input-minimizes spurious content critical in diversity radio receivers and test equipment. |
| Analog Bandwidth | 650 MHz-preserves signal integrity for wideband IF sampling without external amplification. |
| Power Consumption | 331 mW total (four channels, sine wave input, ANSI-644 mode)-enables compact, thermally constrained PCB layouts. |
| Supply Voltage | 1.8 V AVDD/DRVDD-simplifies power delivery with single low-noise LDO, eliminating need for multiple rails. |
| Operating Temperature | −40°C to +85°C-qualified for industrial and medical equipment deployed in uncontrolled environments. |
Pinout & Package
AD9633BCPZ-80 is housed in a RoHS-compliant, 48-lead LFCSP (7 mm × 7 mm, CP-48-13), with exposed thermal pad (Pin 0, AGND) soldered to PCB ground for optimal thermal and analog performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+A / VIN−A | ADC A differential analog input | Accepts 2 V p-p differential signal; common-mode voltage set externally via VCM pin (0.9 V nominal). |
| CLK+ / CLK− | Differential encode clock input | Supports LVDS/LVPECL/CMOS; enables jitter-insensitive sampling with 135 fs rms aperture uncertainty. |
| D0+A / D0−A, D1+A / D1−A | Channel A LVDS data outputs (two-lane mode) | Deliver serialized 12-bit DDR data; disabled in one-lane configuration per Register 0x21 Bits[6:4]. |
| DCO+ / DCO− | Data clock output | Provides source-synchronous capture clock up to 375 MHz; phase-aligned to data with ±300 ps delay tolerance. |
| FCO+ / FCO− | Frame clock output | Signals start of each output byte; used for multichip synchronization and data framing in FPGA receivers. |
| SCLK / SDIO / CSB | SPI serial port interface | 3-wire configuration bus for register writes/reads; supports custom test pattern loading and power mode control. |
| PDWN | Global power-down control | Active-high input; reduces total power to 2 mW when asserted-critical for burst-mode acquisition systems. |
| SYNC | Multi-device clock divider sync | Enables deterministic phase alignment across multiple AD9633 devices in time-coherent array systems. |
Key Features
| Feature | Design Value |
|---|---|
| Quad-channel integration in 7 mm × 7 mm LFCSP | Reduces board area by >60% vs. discrete dual-channel ADC solutions-ideal for portable ultrasound probes. |
| Programmable output resolution (10/12-bit) | Lowers data throughput and FPGA resource usage in applications where ENOB >10 bits suffices. |
| Built-in deterministic and pseudorandom test patterns | Eliminates need for external pattern generators during production test and system bring-up. |
| Individual-channel power-down | Enables dynamic channel gating in phased-array systems-reducing power by ~100 mW per disabled channel. |
| Flexible bit orientation and data alignment | Allows seamless interface with Xilinx/Kintex or Intel/Arria FPGA transceivers without custom logic. |
| Standby mode (174 mW) | Provides rapid wake-up (<250 ns) while retaining configuration-suitable for duty-cycled radar receivers. |
Applications
| Medical Ultrasound Imaging | High-Speed Industrial Imaging |
|---|---|
|
Use Scenario: Digitizing RF echo signals from 128+ element transducer arrays in portable ultrasound machines. IC Role / Device Role / Timing Role: Quad ADC front-end converting four parallel analog beam paths into synchronized LVDS data streams for FPGA-based beamforming. Use Value: 71 dB SNR and 96 dBc SFDR preserve tissue contrast and lesion detectability; 80 MSPS sample rate supports 40 MHz receive bandwidth. |
Use Scenario: Capturing high-frame-rate images from line-scan cameras in automated optical inspection (AOI) systems. IC Role / Device Role / Timing Role: Simultaneous digitization of four analog camera outputs with deterministic latency (16 clock cycles pipeline) for real-time defect analysis. Use Value: 650 MHz analog bandwidth accommodates sharp-edged square-wave pixel signals; LVDS serialization reduces routing congestion on dense sensor boards. |
| Quadrature Radio Receivers | Automated Test Equipment (ATE) |
|
Use Scenario: I/Q downconversion in diversity LTE/Wi-Fi receivers requiring phase-coherent sampling of RF/IF signals. IC Role / Device Role / Timing Role: Four-channel ADC capturing in-phase and quadrature components with multichip sync (SYNC pin) for coherent MIMO processing. Use Value: <135 fs rms aperture jitter ensures <0.1° phase error at 100 MHz; −95 dB crosstalk prevents inter-channel interference in adjacent antennas. |
Use Scenario: High-accuracy waveform digitization in modular ATE platforms performing parametric testing of RF ICs. IC Role / Device Role / Timing Role: Precision digitizer channel supporting swept-frequency measurements up to 200 MHz with calibrated ENOB tracking. Use Value: 11.6-bit ENOB at 9.7 MHz and stable gain matching (±2.14% FSR) enable traceable measurement uncertainty budgets per IEEE 1651. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel, 12-bit, serial-output ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9633BCPZ-105 | Higher 105 MSPS sample rate; higher power (389 mW); identical pinout and SPI register map. | Required for IF sampling above 40 MHz or wider instantaneous bandwidth in spectrum analyzers. | Select AD9633BCPZ-105 only if system timing budget requires >80 MSPS-no layout change needed. |
| AD9253BCPZ-80 | 14-bit resolution, same 80 MSPS rate, pin-compatible but higher power (450 mW); different INL/DNL specs. | Suitable where 14-bit ENOB is mandatory (e.g., high-fidelity audio test), but not for SNR-constrained RF apps. | Choose AD9253BCPZ-80 when resolution outweighs power and SFDR trade-offs-same footprint, revised decoupling. |
Compared with AD9633BCPZ-105 and AD9253BCPZ-80, the AD9633BCPZ-80 delivers optimal balance of 12-bit precision, 71 dB SNR, and 331 mW power in space-constrained medical and test systems-without requiring PCB redesign or firmware rework.
Availability
AD9633BCPZ-80 is available at Aetrix Electronics and suitable for medical ultrasound imaging, high-speed industrial inspection, quadrature radio receivers, and automated test equipment requiring stable component supply across multi-year production cycles.
Supply support for AD9633BCPZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.
The AD9633 product line delivers quad-channel, low-power, high-SNR ADCs optimized for space-constrained, thermally sensitive applications including portable diagnostics and software-defined radio infrastructure.
FAQ
What is the maximum analog input frequency supported by the AD9633BCPZ-80?
The AD9633BCPZ-80 features a 650 MHz full-power analog bandwidth, enabling accurate digitization of input signals up to 200 MHz while maintaining ≥69.4 dB SNR. This specification is measured under standard conditions (2 V p-p differential input, −1.0 dBFS, 25°C) and supports undersampling architectures in communications and instrumentation applications.
Does the AD9633BCPZ-80 require an external voltage reference?
No, the AD9633BCPZ-80 includes an internal 1.0 V reference with ±2% accuracy over temperature and load. The VREF pin serves as both input and output; it can be bypassed with a 0.1 µF capacitor or driven externally to override the internal reference-enabling system-level calibration or ratiometric measurement schemes.
How does the SPI interface of the AD9633BCPZ-80 support configuration and test?
The AD9633BCPZ-80 uses a 3-wire SPI (SCLK, SDIO, CSB) to access a memory-mapped register set for configuring output format, power modes, test patterns, and clock alignment. It supports readback of status registers and loading of user-defined digital test patterns-eliminating need for external pattern generators during validation.
What thermal management is required for the AD9633BCPZ-80 in continuous operation?
The AD9633BCPZ-80 has θJA = 23.7°C/W (0 m/sec airflow) on a 4-layer PCB with solid ground plane. Its exposed thermal pad (Pin 0, AGND) must be soldered to a minimum 200 mm² copper pour connected to system ground. For ambient temperatures up to +85°C, this ensures junction temperature remains below 150°C at full 331 mW power dissipation.
Can the AD9633BCPZ-80 operate in single-lane LVDS mode?
Yes, the AD9633BCPZ-80 supports one-lane LVDS output mode via Register 0x21 Bits[6:4], repurposing pins D0−A/D0+A and D1−A/D1+A as channel C outputs. This halves data rate per lane and simplifies FPGA interface but increases per-lane timing margin requirements-verified in Table 4 timing specs for one-lane operation.
AD9633BCPZ-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 48-LFCSP (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9633BCPZ-80 FAQ
1.How can I place an order for AD9633BCPZ-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9633BCPZ-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9633BCPZ-80 reliable?
The price and inventory of AD9633BCPZ-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9633BCPZ-80 is usually 5 days.
3.What payment methods are accepted for AD9633BCPZ-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9633BCPZ-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9633BCPZ-80?
AD9633BCPZ-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9633BCPZ-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9633BCPZ-80?
For technical support, including AD9633BCPZ-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9633BCPZ-80 requirements.
6.How does Aetrix verify that AD9633BCPZ-80 is sourced from the original manufacturer or authorized distributors?
All AD9633BCPZ-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9633BCPZ-80 meets industry standards.
7.What is the process for return or replacement of AD9633BCPZ-80?
All AD9633BCPZ-80 units undergo pre-shipment inspection (PSI). If there is an issue with AD9633BCPZ-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9633BCPZ-80 part is unused and in its original packaging.
Return procedure for AD9633BCPZ-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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