Analog Devices Inc. AD9635-125EBZ

Overview

AD9635-125EBZ from Analog Devices is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter evaluation board designed to demonstrate the performance of the AD9635-125 ADC in serial LVDS output mode. It supports full-speed data capture with 650 MHz analog input bandwidth, 71 dBFS SNR at 70 MHz input, and programmable output alignment-enabling rapid validation in communications receivers, radar front ends, and portable ultrasound systems.

For engineers reviewing the AD9635-125EBZ datasheet, AD9635-125EBZ pinout, AD9635-125EBZ application, or AD9635-125EBZ equivalent, this board provides direct access to the AD9635-125's serial LVDS outputs, SPI-configurable timing alignment, clock divider, and built-in test pattern generation-critical for verifying high-speed data interface integrity, channel matching, and low-power operation in battery-powered instrumentation and diversity radio systems.

Technical Context

The AD9635-125EBZ implements the AD9635-125 IC in a 32-lead LFCSP package with exposed paddle thermal grounding, supporting dual-channel simultaneous sampling at up to 125 MSPS with 1.8 V AVDD/DRVDD supplies. Its on-board clock conditioning circuitry accepts LVPECL/LVDS/CMOS inputs and generates synchronized DCO/FCO signals for DDR data capture.

Board-level features include configurable termination for LVDS lanes (ANSI-644 or reduced-range), selectable input coupling (AC/DC), onboard VCM and reference decoupling, and SPI interface routing to an external controller-enabling real-time register control of output resolution (10/12-bit), bit orientation, power-down modes, and digital test patterns without modifying hardware.

Key Specifications

Availability

AD9635-125EBZ is available at Aetrix Electronics and suitable for communications receiver development, radar/LIDAR signal acquisition, and portable medical imaging requiring stable component supply, traceable evaluation hardware, and documented reference design support.

Supply support for AD9635-125EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, industrial, and aerospace markets.

The AD9635-125EBZ belongs to Analog Devices' high-speed ADC evaluation platform family, engineered to accelerate prototyping of wideband digitization systems where dynamic range, low power, and small form factor are critical-especially in diversity radio, smart antenna, and battery-powered test equipment.

FAQ

What is the primary function of the AD9635-125EBZ evaluation board?

The AD9635-125EBZ is a dedicated evaluation platform for the AD9635-125 dual 12-bit 125 MSPS ADC. It provides complete signal chain access-including analog inputs, LVDS data outputs, DCO/FCO clocks, and SPI control-to validate dynamic performance, interface timing, and system-level integration without custom PCB design. The board enables immediate characterization of SNR, SFDR, and channel matching under real-world clock jitter and signal conditions.

Does the AD9635-125EBZ support both ANSI-644 and reduced-range LVDS output modes?

Yes, the AD9635-125EBZ supports both LVDS output standards via onboard jumper-selectable termination networks. In ANSI-644 mode, it delivers 290–400 mV differential output voltage for robust noise immunity; in reduced-range mode, it operates at 160–230 mV for lower power consumption-matching the AD9635-125's internal driver capability and enabling optimization for FPGA I/O voltage constraints or thermal budget limits.

Can the AD9635-125EBZ be used with standard FPGA development kits?

Yes, the AD9635-125EBZ features a standardized 20-pin Samtec QSH connector delivering all LVDS data lanes (D0A±, D1A±, D0B±, D1B±), DCO±, FCO±, and SPI signals at 1.8 V logic levels-compatible with Xilinx Kintex/Virtex and Intel Stratix/Cyclone FPGA carrier boards. Its pinout follows industry-standard high-speed ADC interface conventions, and timing parameters (e.g., tDATA = ±300 ps around tSAMPLE/12) are fully documented for accurate constraint entry in synthesis tools.

What clock sources are compatible with the AD9635-125EBZ?

The AD9635-125EBZ accepts differential clock inputs (CLK+/CLK−) compliant with LVPECL, LVDS, or 1.8 V CMOS logic families, with 0.2–3.6 V p-p swing and common-mode voltage centered at 0.9 V. It supports clock frequencies from 10 MHz to 1 GHz, and its onboard biasing eliminates need for external termination or level-shifting-enabling direct connection to signal generators, clock synthesizers like the ADF4351, or FPGA clock outputs.

How does the AD9635-125EBZ handle analog input common-mode voltage (VCM)?

The AD9635-125EBZ routes the AD9635-125's internal VCM pin to a dedicated test point and includes a 0.1 µF decoupling capacitor as specified in the datasheet. Users can either use the internal 0.9 V reference (AVDD/2) for optimal SNR or override it with an external source via the VCM header-supporting both transformer-coupled (AC-coupled) and amplifier-driven (DC-coupled) input configurations while maintaining full 2 V p-p differential input range and <±0.4 LSB INL performance.