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Analog Devices Inc. AD9635BCPZ-80
- Part No.:
- AD9635BCPZ-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad, CSP
- Datasheet:
-
AD9635BCPZ-80.pdf
- Description:
- IC ADC 12BIT PIPELINED 32LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:4,735
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Product details
Overview
AD9635BCPZ-80 from Analog Devices is a dual-channel, 12-bit, 80 MSPS analog-to-digital converter with serial LVDS output, 1.8 V supply operation, 71 dBFS SNR at Nyquist, and 650 MHz full-power analog bandwidth-designed for I/Q demodulation in LTE/W-CDMA receivers and portable ultrasound front-ends.
For engineers reviewing the AD9635BCPZ-80 datasheet, AD9635BCPZ-80 pinout, AD9635BCPZ-80 application, or AD9635BCPZ-80 equivalent, this page delivers verified specifications, validated pin functions, confirmed industrial-temperature operation (−40°C to +85°C), and real-world use cases in diversity radio systems and battery-powered instrumentation.
Technical Context
The AD9635BCPZ-80 implements a multistage pipelined ADC architecture with 1-bit redundancy per stage for digital error correction, sampling on the rising clock edge, and internal digital staging that aligns, corrects, and serializes data before LVDS transmission. It supports both ANSI-644 LVDS and low-power reduced-range LVDS output modes.
It integrates a 1.0 V internal voltage reference, programmable output clock/data alignment, flexible bit orientation (twos complement default), and SPI-configurable features including clock divider, output resolution (10/12-bit), and test pattern generation-enabling deterministic system-level timing control without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit-supports high-fidelity digitization of wideband IF signals up to 200.5 MHz input frequency. |
| Sample Rate | 80 MSPS-fixed maximum conversion rate for this variant; enables real-time capture of 70 MHz RF carriers with >2× Nyquist margin. |
| SNR | 71.2 dBFS (typical, fIN = 70 MHz)-defines usable dynamic range for baseband I/Q processing in multimode receivers. |
| SFDR | 94 dBc (typical, fIN = 70 MHz)-ensures clean spectral separation between desired signal and spurious tones in dense RF environments. |
| Analog Bandwidth | 650 MHz-allows direct sampling of L-band and lower S-band signals without external antialiasing filtering. |
| Power Consumption | 194 mW (two channels, sine input, ANSI-644 mode)-enables thermal-constrained designs in handheld scopes and portable medical imaging. |
| Input Range | 2 V p-p differential-matches standard transformer-coupled front-ends and simplifies driver selection. |
| Supply Voltage | 1.8 V AVDD/DRVDD-reduces power delivery complexity and enables compatibility with modern low-voltage SoC interfaces. |
Pinout & Package
The AD9635BCPZ-80 is housed in a RoHS-compliant, 32-lead LFCSP (5 mm × 5 mm) with exposed paddle soldered to AGND for thermal and noise performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND, Exposed Pad | Analog Ground Reference | Only ground connection; must be soldered to PCB analog ground plane for functional integrity, thermal dissipation, and EMI suppression. |
| CLK+, CLK− | Differential Clock Input | Accepts LVPECL/LVDS/CMOS; defines sampling instant; jitter directly limits achievable SNR. |
| VINA+/VINA−, VINB+/VINB− | Differential Analog Inputs | High-impedance switched-capacitor inputs; require external common-mode bias (VCM = 0.9 V typical) and matching network for >70 MHz operation. |
| D0A±, D1A±, D0B±, D1B± | LVDS Digital Outputs | Two-lane DDR serial output per channel; supports ANSI-644 (345 mV VOD) or reduced-range (200 mV VOD) modes to trade power vs. noise immunity. |
| DCO+, DCO− | Data Clock Output | DDR-aligned clock at fSAMPLE/2; used by FPGA/ASIC to latch serialized data; propagation delay tCPD = 1.5–3.1 ns. |
| FCO+, FCO− | Frame Clock Output | Indicates start of new byte/frame; enables byte-level synchronization across multiple ADCs in time-aligned arrays. |
| SDIO/PDWN | SPI Data I/O / Power-Down Control | Bidirectional SPI interface (30 kΩ pull-down); in non-SPI mode, asserts full chip power-down consuming <2 mW. |
| SCLK/DFS, CSB | SPI Clock / Chip Select | Standard 3-wire SPI interface (CSB active-low, SCLK max 25 MHz); DFS pin selects twos complement (high) or offset binary (low) output coding. |
| VREF, VCM, RBIAS | Reference & Bias Control | VREF = 1.0 V ±2% output; VCM sets analog input common-mode (0.9 V typical); RBIAS connects to 10 kΩ resistor to set internal bias current. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Output Resolution | Configurable 10-bit or 12-bit output via SPI-reduces FPGA resource usage and SerDes bandwidth when full resolution is unnecessary. |
| Individual Channel Power-Down | Each ADC core can be disabled independently-enables dynamic power scaling in diversity receiver architectures with asymmetric channel loading. |
| Built-in Digital Test Patterns | Includes deterministic, pseudorandom, and user-defined patterns loaded via SPI-eliminates need for external pattern generators during board-level validation. |
| Flexible Bit Orientation | Twos complement (default) or offset binary selectable via DFS pin or SPI-simplifies integration with DSPs requiring specific data formats. |
| Serial Port Control (SPI) | Full register access for clock divider, output alignment, test modes, and power states-enables runtime reconfiguration without hardware changes. |
| Standby Mode | Low-latency wake-up (250 ns) from standby-preserves configuration while reducing power to 99 mW, ideal for burst-mode radar/LIDAR acquisition. |
Applications
| Communications Receiver | Portable Ultrasound Front-End |
|---|---|
Use Scenario: Multimode digital receiver in LTE/W-CDMA base station remote radio head with space-constrained RF module. IC Role / Device Role / Timing Role: Dual-channel ADC digitizing I/Q downconverted signals at 80 MSPS with synchronized frame clock for FPGA-based digital downconversion. Use Value: 71 dBFS SNR and 94 dBc SFDR enable detection of weak adjacent-channel signals in crowded spectrum; 32-lead LFCSP saves PCB area versus discrete dual-ADC solutions. | Use Scenario: Handheld ultrasound probe with integrated beamformer requiring low-power, high-linearity digitization of 5–15 MHz echo signals. IC Role / Device Role / Timing Role: Dual ADC capturing analog beamformed RF echoes with precise inter-channel phase matching for coherent beam steering. Use Value: ±0.4 LSB INL and −40°C to +85°C rating ensure consistent image quality across clinical environments; 194 mW total power enables battery operation >4 hours. |
| Smart Antenna System | Battery-Powered Spectrum Analyzer |
Use Scenario: 4-element adaptive antenna array in 5G small cell with independent RF chains per element. IC Role / Device Role / Timing Role: One AD9635BCPZ-80 per RF path digitizing baseband I/Q outputs; FCO outputs aligned across all units for time-coherent channel estimation. Use Value: Individual channel power-down allows dynamic channel gating during calibration; 650 MHz analog bandwidth supports wide instantaneous bandwidth for angle-of-arrival estimation. | Use Scenario: Field-deployable handheld spectrum analyzer covering 10 kHz–1 GHz with real-time FFT processing. IC Role / Device Role / Timing Role: ADC sampling at 80 MSPS with programmable clock divider to support variable RBW settings; serial LVDS reduces routing complexity on compact PCB. Use Value: Low 174 fs rms aperture jitter preserves frequency domain resolution; 1.8 V supply simplifies single-cell Li-ion power architecture with minimal DC/DC stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 12-bit, 80 MSPS ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9635BCPZ-125 | Higher sample rate (125 MSPS), higher power (245 mW), identical pinout and feature set. | Required for wider instantaneous bandwidth (>100 MHz) or higher IF sampling; not drop-in due to increased thermal load and clock timing constraints. | Select AD9635BCPZ-125 only if system demands >80 MSPS throughput; AD9635BCPZ-80 remains optimal for thermal- or power-constrained 70 MHz IF applications. |
| AD9645BCPZ-80 | 14-bit resolution, same 80 MSPS rate, pin-compatible but higher power (320 mW), no reduced-range LVDS option. | Used where ENOB >11.5 bits is mandatory (e.g., high-fidelity radar pulse analysis); requires revised power delivery and layout for higher current draw. | Choose AD9645BCPZ-80 when quantization noise floor must be lowered by ≥6 dB; AD9635BCPZ-80 offers better power efficiency for SNR-critical but resolution-sufficient applications. |
Compared with AD9635BCPZ-125 and AD9645BCPZ-80, the AD9635BCPZ-80 delivers optimal balance of 71 dBFS SNR, 194 mW power, and 32-lead LFCSP footprint-making it the preferred choice for thermally constrained, battery-operated, or cost-sensitive dual-channel digitization where 12-bit resolution meets system requirements.
Availability
AD9635BCPZ-80 is available at Aetrix Electronics and suitable for communications receivers, portable medical imaging, smart antenna systems, and battery-powered instrumentation requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for AD9635BCPZ-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The AD9635 product line delivers dual-channel, low-power, high-speed ADCs optimized for space-constrained, thermally sensitive applications in wireless infrastructure, portable test equipment, and medical ultrasound-emphasizing ease of use through integrated references, flexible digital interfaces, and robust AC performance.
FAQ
What is the maximum analog input frequency supported by the AD9635BCPZ-80?
The AD9635BCPZ-80 has a full-power analog bandwidth of 650 MHz, enabling direct sampling of RF signals up to 200.5 MHz while maintaining 68.4 dBFS SNR. This bandwidth supports L-band and lower S-band applications without external antialiasing filters, though system-level anti-imaging filtering may still be required depending on the Nyquist zone.
Does the AD9635BCPZ-80 require an external voltage reference?
No, the AD9635BCPZ-80 integrates a stable 1.0 V internal voltage reference accessible at the VREF pin. External decoupling with a 1.0 μF and 0.1 μF ceramic capacitor is required, but no external reference IC or trimming is needed-reducing BOM count and layout complexity for most applications.
How does the AD9635BCPZ-80 handle power management in portable systems?
The AD9635BCPZ-80 supports three low-power states: standby mode (99 mW), individual channel power-down, and full chip power-down (<2 mW). These are controlled via SPI or static pins (SDIO/PDWN, DFS), enabling dynamic power scaling in battery-powered instruments like handheld scopes and portable ultrasound devices.
Can the AD9635BCPZ-80 output data in offset binary format?
Yes, the AD9635BCPZ-80 supports both twos complement (default) and offset binary output coding. The format is selected either by driving the DFS pin high (twos complement) or low (offset binary), or programmatically via SPI register configuration-providing flexibility for interfacing with legacy DSPs or FPGAs requiring specific data formats.
What LVDS standards does the AD9635BCPZ-80 comply with?
The AD9635BCPZ-80 supports two LVDS output modes: ANSI-644 compliant (345 mV typical differential output voltage) and a low-power reduced-range option (200 mV typical VOD) similar to IEEE 1596.3. Both modes maintain signal integrity over standard FR-4 PCB traces up to 15 cm, with the reduced-range mode lowering power by ~15% at the cost of noise margin.
AD9635BCPZ-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-LFCSP (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
AD9635BCPZ-80 FAQ
1.How can I place an order for AD9635BCPZ-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for AD9635BCPZ-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AD9635BCPZ-80 reliable?
The price and inventory of AD9635BCPZ-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AD9635BCPZ-80 is usually 5 days.
3.What payment methods are accepted for AD9635BCPZ-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AD9635BCPZ-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AD9635BCPZ-80?
AD9635BCPZ-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AD9635BCPZ-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AD9635BCPZ-80?
For technical support, including AD9635BCPZ-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AD9635BCPZ-80 requirements.
6.How does Aetrix verify that AD9635BCPZ-80 is sourced from the original manufacturer or authorized distributors?
All AD9635BCPZ-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AD9635BCPZ-80 meets industry standards.
7.What is the process for return or replacement of AD9635BCPZ-80?
All AD9635BCPZ-80 units undergo pre-shipment inspection (PSI). If there is an issue with AD9635BCPZ-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AD9635BCPZ-80 part is unused and in its original packaging.
Return procedure for AD9635BCPZ-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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