Analog Devices Inc. AD9635BCPZRL7-80

Overview

AD9635BCPZRL7-80 from Analog Devices is a dual-channel, 12-bit, 80 MSPS serial LVDS analog-to-digital converter operating from a single 1.8 V supply. It delivers 71.2 dBFS SNR at 70 MHz input and 94 dBc SFDR (typ), with 650 MHz full-power analog bandwidth and 2 V p-p differential input range. It serves as the front-end digitizer in multiband wireless receivers and portable ultrasound systems.

For engineers reviewing the AD9635BCPZRL7-80 datasheet, AD9635BCPZRL7-80 pinout, AD9635BCPZRL7-80 application, or AD9635BCPZRL7-80 equivalent, this page provides verified specifications, validated pin functions, confirmed industrial-temperature operation (−40°C to +85°C), real-world AC performance data at 80 MSPS, and two rigorously cross-checked alternative parts for diversity radio and I/Q demodulation designs.

Technical Context

The AD9635BCPZRL7-80 implements a multistage pipelined ADC architecture with 1-bit redundancy per stage for digital error correction and 16-clock-cycle pipeline latency. It integrates on-chip 1.0 V reference, programmable clock divider, and dual independent power-down modes-enabling sub-2 mW full chip shutdown.

Its serial LVDS output supports ANSI-644 (345 mV typical VOD) or low-power reduced-range mode (200 mV typical VOD), with DCO and FCO outputs synchronized to DDR data framing. Input common-mode voltage is set via dedicated VCM pin (0.9 V nominal), and analog inputs accept 2 V p-p differential signals with 3.5 pF capacitance and 5.2 kΩ resistance.

Key Specifications

Pinout & Package

The AD9635BCPZRL7-80 is housed in a RoHS-compliant, 32-lead LFCSP (5 mm × 5 mm) with exposed paddle soldered to AGND for thermal and noise integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, 80 MSPS ADC applications.

Compared with AD9635BCPZRL7-80, AD9645BCPZRL7-80 offers higher resolution at increased power and cost, while ADS52J90IRGCT provides a lower-resolution, lower-cost alternative in a non-pin-compatible package-making AD9635BCPZRL7-80 the optimal balance of 12-bit fidelity, 80 MSPS speed, and 194 mW power in compact LFCSP for industrial wireless and medical edge devices.

Availability

AD9635BCPZRL7-80 is available at Aetrix Electronics and suitable for wireless infrastructure, portable medical imaging, and handheld test equipment requiring stable component supply across extended product lifecycles.

Supply support for AD9635BCPZRL7-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The AD9635 belongs to Analog Devices' high-speed data converter product line, engineered specifically for demanding communications, instrumentation, and medical imaging applications requiring low power, small footprint, and exceptional dynamic range at 80–125 MSPS rates.

FAQ

What is the maximum analog input frequency supported by the AD9635BCPZRL7-80?

The AD9635BCPZRL7-80 features a 650 MHz full-power analog bandwidth, meaning it maintains specified SNR and SFDR performance up to 650 MHz input frequency. This allows direct sampling of L-band radar and UHF signals without intermediate frequency stages. Performance degrades gradually beyond this point, with SNR dropping to 68.4 dBFS at 200.5 MHz and 68.9 dBFS at 139.5 MHz under standard test conditions.

Does the AD9635BCPZRL7-80 require an external voltage reference?

No, the AD9635BCPZRL7-80 integrates a precision 1.0 V internal voltage reference accessible via the VREF pin. External decoupling with a 1.0 μF low-ESR capacitor in parallel with a 0.1 μF ceramic capacitor is mandatory. The reference exhibits ±2 mV load regulation at 1.0 mA and drift of ≤3.7 ppm/°C over temperature-eliminating need for external references in most applications.

How does the AD9635BCPZRL7-80 handle power management in portable systems?

The AD9635BCPZRL7-80 supports three low-power states: standby mode (99 mW), individual channel power-down (<2 mW per channel), and full chip power-down (2 mW). Standby is controlled via SPI; static power-down uses the SDIO/PDWN pin. These modes enable dynamic power scaling in battery-powered instruments like handheld scope meters, extending operational life without sacrificing wake-up latency (250 ns from standby).

Can the AD9635BCPZRL7-80 interface directly with Xilinx or Intel FPGAs?

Yes, the AD9635BCPZRL7-80's LVDS serial outputs (D0x±, D1x±), DCO, and FCO are fully compatible with Xilinx UltraScale+ and Intel Stratix 10 FPGA high-speed transceivers. Its programmable output clock/data alignment and DDR framing simplify timing closure. Reference designs confirm successful interfacing using IBERT and IDELAYE3 primitives for deskew calibration-no external serializer/deserializer required.

What is the purpose of the RBIAS pin on the AD9635BCPZRL7-80?

The RBIAS pin sets the analog bias current for the AD9635BCPZRL7-80's internal pipeline stages. It must be connected to a 10 kΩ (1% tolerance) resistor tied to AGND. Incorrect RBIAS value causes measurable degradation in SNR (up to 2 dB) and SFDR (up to 8 dB), as confirmed in Figure 22 and Figure 39 of the datasheet. This external resistor replaces trim DACs used in older ADC generations, improving process stability.