Analog Devices Inc. AD9640BCPZ-105

Overview

AD9640BCPZ-105 from Analog Devices is a dual-channel, 14-bit, 105 MSPS analog-to-digital converter optimized for IF sampling in communications receivers. It operates from a single 1.8 V analog supply, supports differential analog inputs up to 650 MHz bandwidth, delivers 71.9 dBFS SNR at 70 MHz input, and provides 85 dBc SFDR - enabling high-fidelity digitization in LTE and WCDMA baseband processing.

For engineers reviewing the AD9640BCPZ-105 datasheet, AD9640BCPZ-105 pinout, AD9640BCPZ-105 application, or AD9640BCPZ-105 equivalent, key selection considerations include its 105 MSPS sample rate, dual-channel crosstalk of −95 dB, integrated fast detect and signal monitor blocks, LVDS/CMOS output flexibility, and support for IF sampling up to 450 MHz.

Technical Context

The AD9640BCPZ-105 implements two independent pipelined ADC cores with multistage error correction logic, each featuring wideband differential sample-and-hold amplifiers and an internal 1.0 V voltage reference. Its integer clock divider (1–8) and duty cycle stabilizer enable robust operation with non-50% clock sources across demanding RF front-end environments.

It integrates AGC-enabling functions including four-bit fast detect outputs with sub-cycle latency and a programmable signal monitor block that computes composite magnitude via dedicated serial SPORT output. The device supports simultaneous CMOS (1.8–3.3 V) or LVDS (1.8 V) digital outputs, with configurable data formatting (offset binary, twos complement, gray code).

Key Specifications

Pinout & Package

The AD9640BCPZ-105 is housed in a 64-lead, 9 mm × 9 mm LFCSP package with exposed paddle (EP), requiring soldering to PCB ground plane for thermal and electrical integrity per JEDEC JESD51-7.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 14-bit ADC applications.

Compared with AD9640BCPZ-105, AD9627BCPZ-105 trades 2 bits of resolution for lower cost and power, while AD9680BCPZ-105 replaces parallel interfaces with JESD204B to reduce routing density - both require distinct firmware and layout adaptations despite shared sample rate and package footprint.

Availability

AD9640BCPZ-105 is available at Aetrix Electronics and suitable for LTE base station remote radio heads, WCDMA diversity receivers, and software-defined radio transceivers requiring stable component supply, long-term industrial temperature support (−40°C to +85°C), and guaranteed ADC performance consistency across production lots.

Supply support for AD9640BCPZ-105 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, and aerospace markets with precision data conversion solutions.

The AD9640 product line delivers dual-channel, high-speed ADCs targeting cost-sensitive, size-constrained wireless infrastructure - emphasizing integrated AGC features, flexible output interfaces, and IF sampling capability up to 450 MHz.

FAQ

What is the maximum analog input frequency supported by the AD9640BCPZ-105?

The AD9640BCPZ-105 supports analog input frequencies up to 450 MHz using IF sampling techniques, enabled by its 650 MHz analog input bandwidth and 105 MSPS sample rate. This allows undersampling of RF carriers in the first or second Nyquist zone without aliasing, provided anti-alias filtering meets system requirements. The device maintains 71.9 dBFS SNR at 70 MHz and 70.3 dBFS at 200 MHz input.

Does the AD9640BCPZ-105 support both CMOS and LVDS digital outputs simultaneously?

No, the AD9640BCPZ-105 supports either CMOS or LVDS output mode per channel, selected via register configuration and DRVDD supply voltage. CMOS operation requires DRVDD = 1.8 V or 3.3 V; LVDS requires DRVDD = 1.8 V and specific termination. Both modes cannot be active concurrently on the same device - output driver type is globally configured.

How does the fast detect feature of the AD9640BCPZ-105 reduce AGC latency?

The AD9640BCPZ-105 fast detect outputs (FD0A–FD3A/B) deliver 4-bit magnitude information with ≤1 conversion cycle latency - significantly faster than full-data-path processing. This enables immediate gain reduction before overrange occurs, critical for burst-mode systems like TD-SCDMA. The AD9640BCPZ-105 fast detect block operates independently of the main ADC data path and requires no external logic.

Is the AD9640BCPZ-105 pin-compatible with other members of the AD9640 family?

Yes, all AD9640 variants - including AD9640ABCPZ-80, AD9640BCPZ-105, AD9640ABCPZ-125, and AD9640BCPZ-150 - share identical 64-lead LFCSP packaging and pinout. This allows hardware reuse across sample rates; only clocking, power, and register settings differ. The AD9640BCPZ-105 can replace lower-rate versions without PCB modification.

What thermal management is required for the AD9640BCPZ-105 in continuous operation?

The AD9640BCPZ-105 requires its exposed paddle to be soldered to a solid PCB ground plane to achieve θ_JA = 18.8°C/W (still air). Without paddle connection, junction temperature may exceed 150°C at full load (657 mW). Thermal vias under the EP and copper pour on inner layers are recommended; airflow ≥1 m/s further reduces thermal resistance to 16.5°C/W.