Analog Devices Inc. AD9642-170EBZ

Overview

AD9642-170EBZ from Analog Devices is a high-speed analog-to-digital converter evaluation board designed to characterize the AD9642 14-bit, 170 MSPS dual-channel ADC. It supports USB 2.0 data capture via the HSC-ADC-EVALCZ FPGA-based capture board, features anti-aliasing filtering, and enables full-scale testing with low-jitter clock and clean analog signal inputs.

For engineers reviewing the AD9642-170EBZ datasheet, AD9642-170EBZ pinout, AD9642-170EBZ application, or AD9642-170EBZ equivalent, this board provides validated SPI configuration (AD9642_14Bit_250MSspiR03.cfg), VisualAnalog integration, FPGA timing alignment controls (DCO delay, output phase inversion), and hardware-level setup guidance for high-fidelity ADC performance validation.

Technical Context

The AD9642-170EBZ is a dedicated evaluation platform for the AD9642 ADC, requiring co-use with the HSC-ADC-EVALCZ FPGA capture board. It interfaces via USB 2.0 and supports configurable DCO clock delay (600 ps step) and output phase inversion for precise timing alignment between ADC outputs and FPGA sampling.

It accepts analog input through a 50 Ω shielded coaxial connection (J301, Channel A), uses a clean RF clock source (10–14 dBm at J506), and relies on jumper-configured default settings (P104/P105/P107/P108/P110) and 2.5 V FPGA I/O voltage (J9 setting) for operation.

Key Specifications

Availability

AD9642-170EBZ is available at Aetrix Electronics and suitable for high-speed data acquisition systems, RF receiver prototyping, and communications test equipment requiring stable component supply and repeatable ADC characterization workflows.

Supply support for AD9642-170EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies.

The AD9642-170EBZ belongs to Analog Devices' High-Speed Converter Evaluation Platform family, engineered to accelerate validation of precision, wideband ADCs in demanding instrumentation and communications applications.

FAQ

What is the primary function of the AD9642-170EBZ?

The AD9642-170EBZ is an evaluation board specifically designed to assess the performance of the AD9642 14-bit, 170 MSPS dual-channel ADC. It does not operate independently but must be used with the HSC-ADC-EVALCZ FPGA capture board and VisualAnalog software. The AD9642-170EBZ provides analog input conditioning, clock interface, SPI configuration, and physical mounting for controlled lab-based ADC characterization.

Does the AD9642-170EBZ include onboard data storage or processing capability?

No, the AD9642-170EBZ has no onboard memory, processor, or standalone firmware. It functions solely as an interface and signal conditioning platform for the AD9642 ADC. All data capture, formatting, and analysis rely on the companion HSC-ADC-EVALCZ board and host PC running VisualAnalog and SPI Controller software. The AD9642-170EBZ itself performs no digitization or storage.

Which configuration file is required for SPI control of the AD9642-170EBZ?

The AD9642-170EBZ requires the SPI configuration file AD9642_14Bit_250MSspiR03.cfg for proper initialization and register programming. This file is loaded via the SPI Controller software and matches the AD9642's 14-bit, dual-channel architecture. Using an incorrect or mismatched config file-such as one intended for different resolution, sample rate, or date-code variants-will result in improper ADC behavior or failure to initialize the AD9642-170EBZ system.

How is timing alignment managed between the AD9642-170EBZ and the FPGA capture board?

Timing alignment is configured via two SPI-accessible settings in the AD9642-170EBZ's base register map: DCO Clk Delay Enable (FLEXOUTPUT DELAY panel) set to 600 ps additional delay, and O/P Port DCO Clk Invert (OUTPUT PHASE panel), conditionally enabled only for "XCPZ" branded parts with date codes other than 1126. These settings ensure synchronous sampling of ADC output data by the HSC-ADC-EVALCZ FPGA, directly affecting FFT integrity and dynamic performance measurements on the AD9642-170EBZ.

What power supplies are needed to operate the AD9642-170EBZ system?

The AD9642-170EBZ requires one 6 V, 2 A switching power supply (e.g., CUI EPS060250UH-PHP-SZ) connected to its power input. The companion HSC-ADC-EVALCZ board also requires a separate 6 V, 2 A supply, with jumper J9 set to 2.5 V to match FPGA I/O voltage. USB 2.0 provides only data communication-not power-to the AD9642-170EBZ system.